View XC68HC912B32VFU8_8056358.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

m68hc12 microcontrollers freescale.com m68hc12b family data sheet m68hc12b rev. 9.1 07/2005

m68hc12b family data sheet, rev. 9.1 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc., 2005. all rights reserved. m68hc12b family data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com
revision history m68hc12b family data sheet, rev. 9.1 4 freescale semiconductor the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) june, 2001 2.0 figure 1-7. bdm tool connector ? added nc (no connect) designator to pin 3 29 figure 18-16. bdm tool connecto r ? added nc designator to pin 3 305 table 14-2. loop mode functions ? corrected table header, third column, from ddrs1 to dds1 195 woms bit description, fifth line, changed (via ddrs0/2) to (via dds0/2) 195 ssoe bit description, second line, changed ddrs7 to dds7 205 in the table notes following the spc0 bit description, corrected bit designators from ddrs4, ddrs5, ddrs6, and ddrs7 to dds4, dds5, dds6, and dds7. 205 september, 2001 3.0 table 13-3. prescaler selection ? added value column and updated prescale factors 172 19.11 eeprom characteristics ? corrected minimum and maximum values for programming and erase times 313 april, 2002 4.0 document type changed from advance information to technical data reflecting qualification. n/a figure 3-9. condition code register (ccr) ? reset value for s bit corrected from u to 1 62 january, 2003 5.0 14.2.3.3 sci control register 2 ? removed erroneous reference to port s bit 3 in the definition for the transmitter enable bit (te). 197 figure 14-20. port s data register (ports) ? removed erroneous pin function for ps3 and ps2. 208 reformatted to meet publication standards n/a april, 2003 6.0 19.2 maximum ratings ? corrected maximum values for vdd, vdda, vddx, and vin 307 19.7 atd maximum ratings ? correct ed maximum values for vrh and vrl 310 figure 19-1. programming voltage enve lope ? corrected maximum values for vfp and vdd 315 may, 2003 7.0 19.12.1 programming voltage supply envelope ? added subsection for clarity. 315 19.12.2 example v fp protection circuitry ? added subsection for clarity. 316 july, 2003 8.0 19.2 maximum ratings ? updated values 307 19.7 atd maximum ratings ? updated values 310 june, 2004 9.0 table 13-3. prescaler selection ? corrected prescaler factor for values 6 and 7 183 july, 2005 9.1 updated to meet freescale identity guidelines. throughout
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 chapter 2 register block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 chapter 3 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 chapter 4 resets and interr upts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 chapter 5 operating modes and resource mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 chapter 6 bus contro l and input/output (i/o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 chapter 7 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 chapter 8 flash eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 chapter 9 read-only memory (rom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 chapter 10 clock generation m odule (cgm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 chapter 11 pulse-width modulator (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 chapter 12 standard timer (tim). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 chapter 13 enhanced capture ti mer (ect) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 chapter 14 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 91 chapter 15 byte data link communicat ions (bdlc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 chapter 16 mscan12 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 chapter 17 analog-to-digital converter (atd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 chapter 18 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 chapter 19 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 chapter 20 mechanical specificati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
list of chapters m68hc12b family data sheet, rev. 9.1 6 freescale semiconductor
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3 slow-mode clock divider advisory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.4 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6 pinout and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6.1 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6.2 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6.2.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6.2.2 v ddx and v ssx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6.2.3 v dda and v ssa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6.2.4 v rh and v rl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6.2.5 v fp ( mc68hc912b32 and mc68hc912bc32 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6.3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6.3.1 xtal and extal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6.3.2 eclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.6.3.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.6.3.4 irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.6.3.5 xirq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.6.3.6 smodn, moda, and modb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.6.3.7 bkgd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.6.3.8 addr15?addr0 and data15?data0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.6.3.9 r/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.6.3.10 lstrb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.6.3.11 ipipe1 and ipipe0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.6.3.12 dbe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.6.4 port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.6.4.1 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.6.4.2 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6.4.3 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6.4.4 port dlc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.6.4.5 port can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.6.4.6 port ad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.6.4.7 port p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.4.8 port t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.4.9 port s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.5 port pullup, pulldown, and reduced drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
table of contents m68hc12b family data sheet, rev. 9.1 8 freescale semiconductor chapter 2 register block 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 chapter 3 central processor unit (cpu) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.2 programming model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.3.1 accumulators a and b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.3.2 accumulator d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.3.3 index registers x and y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3.4 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3.5 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.3.6 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.4 data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.5 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.6 indexed addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.7 opcodes and operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 chapter 4 resets and interrupts 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.2 exception priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.3 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.4 latching of interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5 interrupt control and priority registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5.1 interrupt control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5.2 highest priority i interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.6 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.6.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.6.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.6.3 computer operating properly (cop) reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.6.4 clock monitor reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.7 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.7.1 operating mode and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.7.2 clock and watchdog control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.7.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.7.4 parallel input/output (i/o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.7.5 central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.7.6 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.7.7 other resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.8 interrupt recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 9 chapter 5 operating modes and resource mapping 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.2.1 normal operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.1.1 normal expanded wide mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.1.2 normal expanded narrow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.1.3 normal single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.2 special operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.2.1 special expanded wide mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.2.2 special expanded narrow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.2.3 special single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.2.4 special peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.2.3 background debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3 internal resource mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.4 mode and resource mapping registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.4.1 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.4.2 register initialization register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4.3 ram initialization register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4.4 eeprom initialization register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.4.5 miscellaneous mapping control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.5 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 chapter 6 bus control and input/output (i/o) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.2 detecting access type from external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.2 port a data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.3 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.4 port b data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.5 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.6 port e data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.7 port e assignment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.8 pullup control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.9 reduced drive of i/o lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 chapter 7 eeprom 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2 eeprom programmer?s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 7.3 eeprom control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.3.1 eeprom module configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.3.2 eeprom block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.3.3 eeprom test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.3.4 eeprom control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
table of contents m68hc12b family data sheet, rev. 9.1 10 freescale semiconductor chapter 8 flash eeprom 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.2 flash eeprom array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3 flash eeprom registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3.1 flash eeprom lock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.3.2 flash eeprom module configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.3.3 flash eeprom module test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.3.4 flash eeprom control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.1 bootstrap operation single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.2 normal operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.3 program/erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.3.1 read/write accesses during program/erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.4.3.2 program/erase verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.4.3.3 program/erase sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.5 programming the flash eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.6 erasing the flash eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 07 8.7 program/erase protection interlocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 09 8.8 stop or wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.9 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 chapter 9 read-only memory (rom) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.2 rom array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 chapter 10 clock generation module (cgm) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.4 clock selection and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.5 slow mode divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.6 clock functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.6.1 computer operating properly (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.6.2 real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.6.3 clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.7 clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.7.1 slow mode divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.7.2 real-time interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.7.3 real-time interrupt flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 19 10.7.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.7.5 arm/reset cop timer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.8 clock divider chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 11 chapter 11 pulse-width modulator (pwm) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.2 pwm register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 11.2.1 pwm clocks and concatenate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 11.2.2 pwm clock select and polarity regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.2.3 pwm enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.2.4 pwm prescale counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.2.5 pwm scale register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.2.6 pwm scale counter 0 value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1 11.2.7 pwm scale register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.2.8 pwm scale counter 1 value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 11.2.9 pwm channel counters 0?3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 11.2.10 pwm channel period registers 0?3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 11.2.11 pwm channel duty registers 0?3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.2.12 pwm control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 11.2.13 pwm special mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 37 11.2.14 port p data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 11.2.15 port p data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11.3 pwm boundary cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11.4 using the output compare 7 feature to generate a pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11.4.1 pwm period calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.4.2 equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.4.3 code listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 chapter 12 standard timer (tim) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.2 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.2.1 timer input capture/output compare select register . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.3.1 timer compare force register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 12.3.2 output compare 7 mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.3.3 output compare 7 data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.3.4 timer count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.3.5 timer system control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 44 12.3.6 timer control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.3.7 timer interrupt mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.3.8 timer interrupt flag registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.3.9 timer input capture/output compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.3.10 pulse accumulator control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.3.11 pulse accumulator flag register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 53 12.3.12 16-bit pulse accumulator count regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.3.13 timer test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.3.14 timer port data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.3.15 data direction register for timer port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 12.4 timer operation in modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
table of contents m68hc12b family data sheet, rev. 9.1 12 freescale semiconductor 12.5 using the output compare function to generate a sq uare wave . . . . . . . . . . . . . . . . . . . . . 156 12.5.1 sample calculation to obtain period counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.5.2 equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.5.3 code listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 chapter 13 enhanced capture timer (ect) module 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.2 basic timer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.3 enhanced capture timer modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.3.1 ic channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.3.1.1 non-buffered ic channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 60 13.3.1.2 buffered ic channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.3.2 pulse accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.3.2.1 pulse accumulator latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.3.2.2 pulse accumulator queue mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.3.3 modulus down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.4 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.4.1 timer input capture/output compare select register . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.4.2 timer compare force register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 13.4.3 output compare 7 mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.4.4 output compare 7 data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13.4.5 timer count registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 13.4.6 timer system control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 68 13.4.7 timer control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 13.4.8 timer interrupt mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.4.9 main timer interrupt flag registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2 13.4.10 timer input capture/output compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.4.11 16-bit pulse accumulator a control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.4.12 pulse accumulator a flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 13.4.13 pulse accumulators count registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 13.4.14 16-bit modulus down-counter control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 13.4.15 16-bit modulus down-counter flag register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.4.16 input control pulse accumulators control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.4.17 delay counter control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.4.18 input control overwrite register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.4.19 input control system control regist er. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.4.20 timer test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 13.4.21 timer port data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 13.4.22 data direction register for timer port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 13.4.23 16-bit pulse accumulator b control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.4.24 pulse accumulator b flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.4.25 8-bit pulse accumulators holding registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 13.4.26 modulus down-counter count registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 13.4.27 timer input capture holding registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 13.5 timer and modulus counter operation in different modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 13 chapter 14 serial interface 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 14.2 serial communication interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 92 14.2.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.2.2 sci baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.2.3 sci register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.2.3.1 sci baud rate control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.2.3.2 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.2.3.3 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.2.3.4 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.2.3.5 sci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.2.3.6 sci data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 14.3 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.3.1 spi baud rate generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.3.2 spi operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.3.3 ss output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.3.4 bidirectional mode (momi or siso). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 14.3.5 spi register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 14.3.5.1 spi control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 14.3.5.2 spi control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14.3.5.3 spi baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.3.5.4 spi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.3.5.5 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.4 port s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 14.4.1 port s data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 14.4.2 port s data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 14.4.3 pullup and reduced drive register for port s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 14.5 serial character transmission using the sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 14.5.1 equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 14.5.2 code listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 14.6 synchronous character transmission using the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 14.6.1 equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 14.6.2 code listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 chapter 15 byte data link communications (bdlc) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 15.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 15.4 bdlc operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 15.4.1 power off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 15.4.2 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 15.4.3 run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 15.5 power-conserving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 15.5.1 bdlc wait and cpu wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 15.5.2 bdlc stop and cpu wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
table of contents m68hc12b family data sheet, rev. 9.1 14 freescale semiconductor 15.5.3 bdlc stop and cpu stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 15.6 loopback modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 15.6.0.1 digital loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 15.6.0.2 analog loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 15.7 bdlc mux interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 15.7.1 rx digital filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 15.7.1.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 15.7.1.2 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 15.7.2 j1850 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 15.7.2.1 sof ? start-of-frame symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 15.7.2.2 data ? in-message data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.7.2.3 crc ? cyclical redundancy check byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.7.2.4 eod ? end-of-data symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.7.2.5 ifr ? in-frame re sponse bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.7.2.6 eof ? end-of-frame symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.7.2.7 ifs ? interframe separation symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.7.2.8 break ? break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 15.7.2.9 idle ? idle bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 15.7.3 j1850 vpw symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 15.7.3.1 logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15.7.3.2 logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15.7.3.3 normalization bit (nb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15.7.3.4 break signal (break) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15.7.3.5 start-of-frame symbol (sof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 15.7.3.6 end-of-data symbol (eod) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 15.7.3.7 end-of-frame symbol (eof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 15.7.3.8 inter-frame separation symbol (ifs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 15.7.3.9 idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 15.7.4 j1850 vpw valid/invalid bits and symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 15.7.4.1 invalid passive bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 15.7.4.2 valid passive logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 15.7.4.3 valid passive logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 15.7.4.4 valid eod symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 15.7.4.5 valid eof and ifs symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 15.7.4.6 idle bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 15.7.4.7 invalid active bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.7.4.8 valid active logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.7.4.9 valid active logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.7.4.10 valid sof symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.7.4.11 valid break symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.7.5 message arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.8 bdlc protocol handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 15.8.1 protocol architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 15.8.2 rx and tx shift registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 15.8.3 rx and tx shadow registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 28 15.8.4 digital loopback multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 15 15.8.5 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 15.8.5.1 4x mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 15.8.5.2 receiving a message in block mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 15.8.5.3 transmitting a message in block mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 15.8.5.4 j1850 bus errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 15.8.5.5 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 15.9 bdlc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 15.9.1 bdlc control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 15.9.2 bdlc control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 15.9.3 bdlc state vector register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.9.4 bdlc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.9.5 bdlc analog roundtrip delay register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.9.6 port dlc control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 15.9.7 port dlc data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15.9.8 port dlc data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2 chapter 16 mscan12 controller 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.2 external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.3 message storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.3.1 background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.3.2 receive structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 16.3.3 transmit structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 16.4 identifier acceptance filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 16.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 16.5.1 interrupt acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 16.5.2 interrupt vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 16.6 protocol violation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 16.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 16.7.1 mscan12 sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 16.7.2 mscan12 soft-reset mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 16.7.3 mscan12 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16.7.4 programmable wakeup function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16.8 timer link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16.9 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16.10 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.11 programmer?s model of message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.11.1 message buffer organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.11.2 identifier registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 16.11.3 data length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 16.11.4 data segment registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 16.11.5 transmit buffer priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 16.12 programmer?s model of control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.12.1 mscan12 module control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.12.2 mscan12 module control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 16.12.3 mscan12 bus timing register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
table of contents m68hc12b family data sheet, rev. 9.1 16 freescale semiconductor 16.12.4 mscan12 bus timing register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 16.12.5 mscan12 receiver flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 16.12.6 mscan12 receiver interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 16.12.7 mscan12 transmitter flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 16.12.8 mscan12 transmitter control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 16.12.9 mscan12 identifier acceptance cont rol register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 16.12.10 mscan12 receive error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 16.12.11 mscan12 transmit error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 16.12.12 mscan12 identifier acceptance registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 16.12.13 mscan12 identifier mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 16.12.14 mscan12 port can control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 16.12.15 mscan12 port can data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 16.12.16 mscan12 port can data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 chapter 17 analog-to-digital converter (atd) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 17.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 17.3 atd registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 17.3.1 atd control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 17.3.2 atd control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 17.3.3 atd control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 17.3.4 adt control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 17.3.5 atd control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 17.3.6 atd control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 17.3.7 atd status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 17.3.8 atd test registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 17.3.9 port ad data input register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 17.3.10 atd result registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 17.4 atd mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 17.5 using the atd to measure a potentiometer signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 17.5.1 equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 17.5.2 code listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 chapter 18 development support 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 18.2 instruction queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 18.3 background debug mode (bdm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 0 18.3.1 bdm serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 18.3.2 enabling bdm firmware commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 18.3.3 bdm commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 18.3.4 bdm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 18.3.5 bdm instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 18.3.5.1 hardware command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 18.3.5.2 firmware command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 17 18.3.6 bdm status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 18.3.7 bdm shifter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 18.3.8 bdm address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 18.3.9 bdm ccr holding register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 99 18.4 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 18.4.1 breakpoint modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 18.4.1.1 swi dual address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 00 18.4.1.2 bdm full breakpoint mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 00 18.4.1.3 bdm dual address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 0 18.4.2 breakpoint registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 18.4.2.1 breakpoint control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 01 18.4.2.2 breakpoint control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 02 18.4.2.3 breakpoint address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 18.4.2.4 breakpoint address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 18.4.2.5 breakpoint data register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 18.4.2.6 breakpoint data register low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 18.5 instruction tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 chapter 19 electrical specifications 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 19.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 19.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19.5 5.0 volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 19.6 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 19.7 atd maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 19.8 atd dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 19.9 analog converter operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 19.10 atd ac operating characteristics (operating) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 19.11 eeprom characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 19.12 flash eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 14 19.12.1 programming voltage supply envelope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 19.12.2 example v fp protection circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 19.13 pulse-width modulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 19.14 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 19.15 peripheral port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 19.16 multiplexed expansion bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 19.17 serial peripheral interface (spi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 chapter 20 mechanical specifications 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 20.2 80-pin quad flat pack (case 841b-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
table of contents m68hc12b family data sheet, rev. 9.1 18 freescale semiconductor
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 19 chapter 1 general description 1.1 introduction the mc68hc912b32, mc68hc12be32 and mc68hc( 9)12bc32, are 16-bit microcontroller units (mcus) composed of standard on-chip peripherals. the multiplexed external bus can also operate in an 8-bit narrow mode for interfacing with single 8-bit wide memory in lower-cost systems. there is a slight feature set difference between the four pin- for-pin compatible devices as shown in table 1-1 . table 1-1. m68hc12b series feature set comparisons features mc68hc912b32 mc68hc12be32 mc68hc912bc32 mc68hc12bc32 cpu12 x x x x multiplexed bus x x x x 32-kbyte flash electrically erasable, programmable read-only memory (eeprom) xx 32-kbyte read-only memory (rom) x x 768-byte eeprom x x x x 1-kbyte random-access memory (ram) x x x x analog-to-digital (a/d) converter x x x x standard timer module (tim) x x x enhanced capture timer (ect) x pulse-width modulator (pwm) x x x x asynchronous serial communications interface (scii) xx x x synchronous serial peripheral interface (spi) x x x x j1850 byte data link communication (bdlc) x x controller area network module (can) x x computer operating properly (cop) watchdog timer xx x x slow mode clock divider x x x x 80-pin quad flat pack (qfp) x x x x single-wire background debug mode (bdm) x x x x
general description m68hc12b family data sheet, rev. 9.1 20 freescale semiconductor 1.2 features features include: 16-bit cpu12: ? upwardly compatible with the m68hc11 instruction set ? interrupt stacking and programmer? s model identical to the m68hc11 ? 20-bit arithmetic logic unit (alu) ? instruction queue ? enhanced indexed addressing ? fuzzy logic instructions multiplexed bus: ? single chip or expanded ? 16-bit by 16-bit wide or 16-bit by 8-bit narrow modes memory: ? 32-kbyte flash electrically erasable, pr ogrammable read-only memory (eeprom) with 2-kbyte erase-protected boot block ? mc68hc912b32 and mc68hc912bc32 only ? 32-kbyte rom ? mc68hc12be32 and mc68hc12bc32 only ? 768-byte eeprom ? 1-kbyte random-access memory (ram) with si ngle-cycle access for aligned or misaligned read/write 8-channel, 10-bit analog-to-digital converter (atd) 8-channel standard timer module (tim) ? mc68hc912b32 and mc68hc(9)12bc32 only: ? each channel fully configur able as either input capture or output compare ? simple pulse-width modulator (pwm) mode ? modulus reset of timer counter enhanced capture timer (ect) ? mc68hc12be32 only: ? 16-bit main counter with 7-bit prescaler ? eight programmable input capture or output com pare channels; four of the eight input captures with buffer ? input capture filters and buffers, three successive captures on four channels, or two captures on four channels with a capture/compare selectable on the remaining four ? four 8-bit or two 16-bit pulse accumulators ? 16-bit modulus down-counter with 4-bit prescaler ? four user-selectable delay counters for signal filtering 16-bit pulse accumulator: ? external event counting ? gated time accumulation pulse-width modulator (pwm): ? 8-bit, 4-channel or 16-bit, 2-channel ? separate control for each pulse width and duty cycle ? programmable center-aligned or left-aligned outputs
slow-mode clock divider advisory m68hc12b family data sheet, rev. 9.1 freescale semiconductor 21 serial interfaces: ? asynchronous serial communications interface (sci) ? synchronous serial peripheral interface (spi) ? j1850 byte data link communication (bdlc), mc68hc912b32 and mc68hc12be32 only ? controller area network (can), mc68hc(9)12bc32 only computer operating properly (cop) watchdog timer, clock monitor, and periodic interrupt timer slow-mode clock divider 80-pin quad flat pack (qfp) up to 63 general-purpose input/output (i/o) lines single-wire background debug mode (bdm) on-chip hardware breakpoints 1.3 slow-mode clock divider advisory current versions of the m68hc12b-series devices incl ude a slow-mode clock divider feature. this feature is fully described in chapter 10 clock gener ation module (cgm) . the register that controls this feature is located at $00e0. older device mask sets do not support the slow-mode clock divider feature. this register address is reserved in olde r devices and provides no function. mask sets that do not have the slow-mode clock di vider feature on the mc68hc912b32 include: g96p, g86w, and h91f. mask sets that do not have the slow-mode clock divi der feature on the mc68hc12be32 include: h54t and j38m. mask sets that do not have the slow-mode clock di vider feature on the mc68hc(9)12bc32 include: j15g.
general description m68hc12b family data sheet, rev. 9.1 22 freescale semiconductor 1.4 block diagrams figure 1-1. block diagram for mc68hc912b32 and mc68hc12be32 ioc0 ioc1 ioc2 ioc3 ioc4 ioc5 ioc6 pai oc7 ddrt port t periodic interrupt cop watchdog 32-kbyte flash eeprom/rom 1-kbyte ram port e timer and pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 spi ddrs port s atd port ad pe1 pe2 pe4 pe5 pe6 pe3 pad3 pad4 pad5 pad6 pad7 v dda v ssa v rh v rl pad0 pad1 pad2 ddra port a ddrb port b pa4 pa3 pa2 pa1 pa0 pa7 pa6 pa5 pb4 pb3 pb2 pb1 pb0 pb7 pb6 pb5 data15 multiplexed address/data bus reset extal xtal pw0 pw1 pw2 pw3 pwm ddrp port p pp0 pp1 pp2 pp3 v dd 2 v ss 2 sci rxd txd i/o i/o sdi/miso sdo/mosi sck cs /ss ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 768-byte eeprom clock monitor pe0 pe7 an3 an4 an5 an6 an7 v dda v ssa v rh v rl an0 an1 an2 single-wire background debug module smodn / taghi eclk r/w lstrb / taglo ipipe0 / moda ipipe1 / modb xirq dbe pulse accumulator lite pp4 pp5 pp6 pp7 i/o i/o i/o i/o i/o i/o dlctx dlcrx i/o bdlc ddrdlc port dlc pdlc4 pdlc5 pdlc6 i/o i/o i/o i/o pdlc0 pdlc1 pdlc2 pdlc3 integration module (lim) v fp break points cpu12 a d d r 1 5 a d d r 1 4 a d d r 1 3 a d d r 1 2 a d d r 1 1 a d d r 1 0 a d d r 9 a d d r 8 data14 data13 data12 data11 data10 data9 data8 a d d r 7 a d d r 6 a d d r 5 a d d r 4 a d d r 3 a d d r 2 a d d r 1 a d d r 0 data7 data6 data5 data4 data3 data2 data1 data0 i/o converter v ssx 2 v ddx 2 power for power for i/o drivers internal circuitry data7 data6 data5 data4 data3 data2 data1 data0 narrow bus wide bus bkgd irq /v pp
block diagrams m68hc12b family data sheet, rev. 9.1 freescale semiconductor 23 figure 1-2. block diagram for mc68hc(9)12bc32 ioc0 ioc1 ioc2 ioc3 ioc4 ioc5 ioc6 pai oc7 ddrt port t periodic interrupt cop watchdog 32-kbyte flash eeprom/rom 1-kbyte ram port e timer and pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 spi ddrs port s atd port ad pe1 pe2 pe4 pe5 pe6 pe3 pad3 pad4 pad5 pad6 pad7 v dda v ssa v rh v rl pad0 pad1 pad2 ddra port a ddrb port b pa4 pa3 pa2 pa1 pa0 pa7 pa6 pa5 pb4 pb3 pb2 pb1 pb0 pb7 pb6 pb5 data15 multiplexed address/data bus reset extal xtal pw0 pw1 pw2 pw3 pwm ddrp port p pp0 pp1 pp2 pp3 v dd 2 v ss 2 sci rxd txd i/o i/o sdi/miso sdo/mosi sck cs /ss ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 768-byte eeprom clock monitor pe0 pe7 an3 an4 an5 an6 an7 v dda v ssa v rh v rl an0 an1 an2 single-wire background debug module smodn / taghi eclk r/w lstrb / taglo ipipe0 / moda ipipe1 / modb xirq dbe pulse accumulator lite pp4 pp5 pp6 pp7 i/o i/o i/o i/o i/o i/o txcan rxcan i/o ddrcan port can pcan4 pcan5 pcan6 i/o i/o i/o i/o rxcan txcan pcan2 pcan3 integration module (lim) v fp break points cpu12 a d d r 1 5 a d d r 1 4 a d d r 1 3 a d d r 1 2 a d d r 1 1 a d d r 1 0 a d d r 9 a d d r 8 data14 data13 data12 data11 data10 data9 data8 a d d r 7 a d d r 6 a d d r 5 a d d r 4 a d d r 3 a d d r 2 a d d r 1 a d d r 0 data7 data6 data5 data4 data3 data2 data1 data0 i/o converter v ssx 2 v ddx 2 power for power for i/o drivers internal circuitry data7 data6 data5 data4 data3 data2 data1 data0 narrow bus wide bus bkgd irq /v pp mscan
general description m68hc12b family data sheet, rev. 9.1 24 freescale semiconductor 1.5 ordering information the m68hc12b-series devices are available in 80- pin quad flat pack (qfp) packaging and are shipped in 2-piece sample packs, 84-pie ce trays, or 420-piece bricks. operating temperature range, package type, and volt age requirements are specified when ordering the specific device. documents to assist in product selection are availabl e from the freescale litera ture distribution center or your local freescale sales offices. product selection guides can also be found on the worldwide web at this url: http://freescale.com evaluation boards, assemblers, compilers, and d ebuggers are available from freescale and from third-party suppliers. an up-to-date list of products t hat support the m68hc12 family of microcontrollers can be found on the worldwide web at this url: http://freescale.com 1.6 pinout and signal descriptions 1.6.1 pin assignments the mcu is available in an 80-pin quad flat pack (qfp). figure 1-3 and figure 1-4 show the pin assignments. most pins perform two or more functions, as described in the 1.6.3 signal descriptions . 1.6.2 power supply pins the mcu power and ground pins are described here and summarized in table 1-2 . 1.6.2.1 v dd and v ss v dd and v ss are the internal power supply and ground pins. because fast signal transitions place high, short-duration current demands on the power s upply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded. 1.6.2.2 v ddx and v ssx v ddx and v ssx are the external power supply and ground pins . because fast signal transitions place high, short-duration current demands on the power s upply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded. 1.6.2.3 v dda and v ssa v dda and v ssa are the power supply and ground pins for the analog-to-digital converter (atd). this allows the supply voltage to be bypassed independently. 1.6.2.4 v rh and v rl v rh and v rl are the reference voltage pins for the atd.
pinout and signal descriptions m68hc12b family data sheet, rev. 9.1 freescale semiconductor 25 figure 1-3. pin assignments for mc68hc912b32 and mc68hc12be32 devices mc68hc912b32 80-pin qfp pp5 pp4 pw3 / pp3 pw2 / pp2 pw1/ pp1 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 pa2 / data10 / addr10 pa3 / data11 / addr11 pa4 / data12 / addr12 pa5 / data13 / addr13 pa6 / data14 / addr14 pa7 / data15 / addr15 pp6 pp7 addr0 / data0 / pb0 addr1 / data1 / pb1 addr2 / data2 / pb2 smodn / taghi / bkgd pai / ioc7 / pt7 ioc6 / pt6 ioc5 / pt5 ioc4 / pt4 ioc3 / pt3 ioc2 / pt2 ioc1 / pt1 ioc0 / pt0 addr9 / data9 / pa1 xirq / pe0 irq / pe1 r/w / pe2 lstrb / taglo / pe3 xtal extal reset v ddx v ssx eclk / pe4 moda / ipipe0 / pe5 modb / ipipe1 / pe6 dbe / pe7 addr7 / data7 / pb7 addr6 / data6 / pb6 addr5 / data5 / pb5 addr4 / data4 / pb4 addr3 / data3 / pb3 v dd v ss pw0/ pp0 v ssa v dda pad7 / an7 pad6 / an6 pad5 / an5 pad4 / an4 pad3 / an3 pad2 / an2 pad1 / an1 pad0 / an0 v rl v rh v ss v dd ps0 / rxd ps1 / txd ps2 ps3 ps4 / sdi/miso ps5 / sdo/mosi ps6 / sck ps7 / cs /ss v fp /nc (1) pdlc6 pdlc5 pdlc4 pdlc3 pdlc2 pdlc1 / dlctx pdlc0 / dlcrx v ssx v ddx addr8 / data8 / pa0 port ad port a (2) port b port e port e port dlc port s port p port t port t shaded pins are power and ground 1. pin 69 is an nc (no connect) on the mc68hc12be32. 2. in narrow mode, high and low data bytes are multiplexed in al ternate bus cycles on port a. notes:
general description m68hc12b family data sheet, rev. 9.1 26 freescale semiconductor figure 1-4. pin assignments for mc68hc(9)12bc32 devices mc68hc(9)12bc32 80-pin qfp pp5 pp4 pw3 / pp3 pw2 / pp2 pw1/ pp1 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 pa2 / data10 / addr10 pa3 / data11 / addr11 pa4 / data12 / addr12 pa5 / data13 / addr13 pa6 / data14 / addr14 pa7 / data15 / addr15 pp6 pp7 addr0 / data0 / pb0 addr1 / data1 / pb1 addr2 / data2 / pb2 smodn / taghi / bkgd pai / ioc7 / pt7 ioc6 / pt6 ioc5 / pt5 ioc4 / pt4 ioc3 / pt3 ioc2 / pt2 ioc1 / pt1 ioc0 / pt0 addr9 / data9 / pa1 xirq / pe0 irq / pe1 r/w / pe2 lstrb / taglo / pe3 xtal extal reset v ddx v ssx eclk / pe4 moda / ipipe0 / pe5 modb / ipipe1 / pe6 dbe / pe7 addr7 / data7 / pb7 addr6 / data6 / pb6 addr5 / data5 / pb5 addr4 / data4 / pb4 addr3 / data3 / pb3 v dd v ss pw0/ pp0 v ssa v dda pad7 / an7 pad6 / an6 pad5 / an5 pad4 / an4 pad3 / an3 pad2 / an2 pad1 / an1 pad0 / an0 v rl v rh v ss v dd ps0 / rxd ps1 / txd ps2 ps3 ps4 / sdi/miso ps5 / sdo/mosi ps6 / sck ps7 / cs /ss v fp /nc (1) pcan6 pcan5 pcan4 pcan3 pcan2 txcan rxcan v ssx v ddx addr8 / data8 / pa0 port ad port a (2) port b port e port e port can port s port p port t port t shaded pins are power and ground 1. pin 69 is an nc (no connect) on the mc68hc12bc32. 2. in narrow mode, high and low data bytes are multiplexed in al ternate bus cycles on port a. notes:
pinout and signal descriptions m68hc12b family data sheet, rev. 9.1 freescale semiconductor 27 1.6.2.5 v fp (mc68hc912b32 and mc68hc912bc32 only) v fp is the flash eeprom programming voltage and su pply voltage during nor mal operation for the mc68hc912b32 and mc68hc912bc32 only. 1.6.3 signal descriptions the mcu signals are described here and summarized in table 1-3 . 1.6.3.1 xtal and extal xtal and extal are the crystal driver and external cl ock input pins. they provide the interface for either a crystal or a cmos compatible clock to control the internal clock generator circuitry. out of reset the frequency applied to extal is twice the desired e-cloc k rate. all the device clocks are derived from the extal input frequency. xtal is the crystal output. the xtal pin must be left unterminated when an external cmos compatible clock input is connected to the extal pin. the xtal output is normally intended to drive only a crystal. the xtal output can be buffered with a high-impedance buffer to drive the extal input of another device. note in all cases, take extra care in the circuit board layout around the oscillator pins. load capacitances shown in the osci llator circuits include all stray layout capacitances. refer to figure 1-5 and figure 1-6 for diagrams of oscillator circuits. table 1-2. power and ground connection summary mnemonic pin number description v dd 10, 47 internal power and ground v ss 11, 48 v ddx 31, 78 external power and ground supply to pin drivers v ssx 30, 77 v dda 59 operating voltage and ground for the atd; allows the supply voltage to be bypassed independently v ssa 60 v rh 49 reference voltages for the analog-to-digital converter v rl 50 v fp 69 programming voltage for the flash eeprom and required supply for normal operation ? mc68hc912b32 and mc68hc912bc32 only. pin 69 is a no connect (nc) on the mc68hc12be32 and mc68hc12bc32.
general description m68hc12b family data sheet, rev. 9.1 28 freescale semiconductor figure 1-5. common crystal connections figure 1-6. external oscillator connections 1.6.3.2 eclk eclk is the output connection for the internal bus clock and is used to demultiplex the address and data and is used as a timing reference. eclk frequency is equal to one half the crystal frequency out of reset. in normal single-chip mode, the e-clock output is off at reset to reduce the effects of radio frequency interference (rfi), but it can be turned on if necessary. in special single-chip mode, the e-clock output is on at reset but can be turned off. in special peripheral mode, the e clock is an input to the mcu. all clocks, including the e clock, are halted when the mcu is in stop mode. it is possible to configure the mcu to interface to slow external memory. eclk can be stretched for such accesses. 1.6.3.3 reset an active-low, bidirecti onal control signal, reset is an input to initialize the mcu to a known startup state. it also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or cop watchdog circuit. the mcu go es into reset asynchronously and comes out of reset synchronously. this allows the part to reach a pr oper reset state even if the clocks have failed, while allowing synchronized operati on when starting out of reset. it is possible to determine whether a reset was caused by an internal source or an external source. an internal source drives the pin low for 16 cycles; eight cycles later, the pin is sampled. if the pin has returned high, either the cop watchdog vector or clock monitor vector is taken. if the pin is still low, the external reset is determined to be active and the reset vector is taken. hold reset low for at least 32 cycles to assure that the reset vector is taken in the event that an internal cop watchdog timeout or clock monitor fail occurs. 1.6.3.4 irq irq is the maskable external interrupt request pin. it provides a means of appl ying asynchronous interrupt requests to the mcu. either falling edge-sensitive triggering or level-sensitive triggering is program 10 m ? mcu c c extal xtal 2 x e crystal nc mcu extal xtal 2 x e cmos-compatible external oscillator
pinout and signal descriptions m68hc12b family data sheet, rev. 9.1 freescale semiconductor 29 selectable (interrupt control register, intcr). irq is always configured to le vel-sensitive triggering at reset. when the mcu is reset, the irq function is masked in the condition code register. this pin is always an input and can always be read. in special modes, it can be used to apply external eeprom v pp in support of eeprom te sting. external v pp is not needed for normal eeprom program and erase cycles. because the irq pin is also used as an eeprom pr ogramming voltage pin, there is an internal resistive pullup on the pin. 1.6.3.5 xirq xirq is the non-maskable external interrupt pin. it provides a means of requesting a non-maskable interrupt after reset initialization. during reset, the x bit in the condition code register (ccr) is set and any interrupt is masked until mcu software enables it. because the xirq input is level sensitive, it can be connected to a multiple-source wired-or network. this pin is always an input and can always be read. there is an active pullup on this pin while in reset and immediately out of reset. the pullup can be turned off by clearing the pupe bit in the pullup control register (pucr). xirq is often used as a power loss detect interrupt. when xirq or irq are used with multiple interrupt sources (irq must be configured for level-sensitive operation if there is more than one source of irq interrupt), each source must drive the interrupt input with an open-drain type of driver to avoid contenti on between outputs. there must also be an interlock mechanism at each interrupt source so that the source holds the interrupt line low until the mcu recognizes and acknowledges the interrupt request. if t he interrupt line is held low, the mcu recognizes another interrupt as soon as the interrupt mask bi t in the mcu is cleared, normally upon return from an interrupt. 1.6.3.6 smodn, moda, and modb smodn, moda, and modb are the mode-select signals. their state during reset determines the mcu operating mode. after reset, moda and modb can be configured as instruction queue tracking signals ipipe0 and ipipe1. moda and modb have active pulldowns during reset. the smodn pin can be used as bkgd or taghi after reset. note to aid in mode selection, refer to figure 1-8 and figure 1-9 . these schematics are provided as suggestive layouts only. 1.6.3.7 bkgd bkgd is the single-wire background mode pin. it re ceives and transmits serial background debugging commands. a special self-timing protocol is used. t he bkgd pin has an active pullup when configured as input; bkgd has no pullup control. currently , the tool connection configuration shown in figure 1-7 is used. figure 1-7. bdm tool connector 2 4 6 5 3 1 reset bkgd v dd gnd v fp nc
general description m68hc12b family data sheet, rev. 9.1 30 freescale semiconductor 1.6.3.8 addr15?addr0 and data15?data0 addr15?addr0 and data15?data0 are the external add ress and data bus pins. they share functions with general-purpose i/o ports a and b. in single-c hip operating modes, the pins can be used for i/o; in expanded modes, the pins are us ed for the external buses. in expanded wide mode, ports a and b multiplex 16-bit data and address buses. the pa7?pa0 pins multiplex addr15?addr8 and data15?data8. th e pb7?pb0 pins mult iplex addr7?addr0 and data7?data0. in expanded narrow mode, ports a and b are used for the 16-bit address bus. an 8-bit data bus is multiplexed with the most significant half of the address bus on port a. in this mode, 16-bit data is handled as two back-to-back bus cycles, one for the high byte followed by one for the low byte. the pa7?pa0 pins multiplex addr15?addr8, data15?data8, and data7?dat a0. the state of the address pin should be latched at the rising edge of e. to allow for maximum address setup time at external devices, a transparent latch should be used. 1.6.3.9 r/w r/w is the read/write pin. in all modes, this pin can be used as input/output (i/o) and is a general-purpose input with an active pullup out of reset. if the read/write function is required, it should be enabled by setting the rdwe bit in the port e assignment register (pear ). external writes are not possible until enabled. 1.6.3.10 lstrb lstrb is the low-byte strobe pin. in all modes, this pin can be used as i/o and is a general-purpose input with an active pullup out of reset. if the strobe f unction is required, it should be enabled by setting the lstre bit in the pear register. this signal is used in write operations and so external low-byte writes are not possible until this function is enabled. this pin is also used as taglo in special expanded modes and is multiplexed with the lstrb function. 1.6.3.11 ipipe1 and ipipe0 ipipe1 and ipipe0 are the instruction queue tracking pins . their signals are used to track the state of the internal instruction execution queue. execution state is time-multiplexed on the two signals. 1.6.3.12 dbe dbe is the data bus enable signal. it is an active-low si gnal that is asserted lo w during e-clock high time. dbe provides separation between output of a multiplexed address and the input of data. when an external address is stretched, dbe is asserted during what would be the last quarter cycle of the last e-clock cycle of stretch. in expanded modes, this pin is used to enable the drive control of external buses during external reads only. use of the dbe is controlled by the ndbe bit in the pear register. dbe is enabled out of reset in expanded modes. this pin has an active pullup during and after reset in single-chip modes.
pinout and signal descriptions m68hc12b family data sheet, rev. 9.1 freescale semiconductor 31 table 1-3. signal description summary pin name pin number description pw3?pw0 3?6 pulse-width modulator channel outputs addr7?addr0 data7?data0 25?18 external bus pins share function with general -purpose i/o ports a and b. in single-chip modes, the pins can be used for i/o. in expanded modes, the pins are used for the external buses. addr15?addr8 data15?data8 46?39 ioc7?ioc0 16?12, 9?7 pins used for input capture and output compare in the timer and pulse accumulator subsystem pai 16 pulse accumulator input an7?an0 58?51 analog inputs for the analog-to-digital conversion module dbe 26 data bus control and, in expanded mode, enables the drive control of external buses during external reads modb, moda 27, 28 state of mode select pins during re set determines the initial operating mode of the mcu. after reset, modb and moda can be configured as instruction queue tracking signals ipipe1 and ipipe0 or as general-purpose i/o pins. ipipe1, ipipe0 27, 28 eclk 29 e-clock is the output connection for the external bus clock. eclk is used as a timing reference and for address demultiplexing. reset 32 an active low bidirecti onal control signal, reset acts as an input to initialize the mcu to a known startup state and an output w hen cop or clock monitor causes a reset. extal 33 crystal driver and external clock input pins. on reset all the device clocks are derived from the extal input frequency. xtal is the crystal output. xtal 34 lstrb 35 low byte strobe (0 = low byte valid), in all modes this pin can be used as i/o. the low strobe function is the exclusive-no r of a0 and the internal sz8 signal. the sz8 internal signal indicates the size 16/8 access. tag l o 35 pin used in instruction tagging r/w 36 indicates direction of data on expansion bus; shares function with general-purpose i/o; read/write in expanded modes irq 37 maskable interrupt request input provides a means of applying asynchronous interrupt requests to the mcu. either falling edge- sensitive triggering or level-sensitive triggering is program selectable (intcr register). xirq 38 provides a means of requesting asynchronous non-maskable interrupt requests after reset initialization bkgd 17 single-wire background interface pin is dedicated to the background debug function. during reset, this pin determines special or normal operating mode. taghi 17 pin used in instruction tagging dlcrx/rxcan (1) 1. the rxcan and txca n designations are for the mc68hc(9)12bc32 only. 76 bdlc receive pin dlctx/txcan (1) 75 bdlc transmit pin cs /ss 68 slave-select output for spi master mode ; input for slave mode or master mode sck 67 serial clock for spi system sdo/mosi 66 master out/slave in pin for serial peripheral interface sdi/miso 65 master in/slave out pin for serial peripheral interface txd0 62 sci transmit pin rxd0 61 sci receive pin
general description m68hc12b family data sheet, rev. 9.1 32 freescale semiconductor 1.6.4 port signals the mcu incorporates eight ports which are used to control and access the various device subsystems. when not used for these purposes, port pins may be used for general-purpose i/o. in addition to the pins described here, each port consists of: a data register which can be read and written at any time with the exception of port ad and pe1?pe0, a data direction register which controls the direction of each pin after reset, all port pins are configured as input. (refer to table 1-4 for a summary of the port signal descriptions.) 1.6.4.1 port a port a pins are used for address and data in expanded m odes. the port data register is not in the address map during expanded and peripheral mode operation. when it is in the map, port a can be read or written at anytime. the port a data direction register (ddra) determines wh ether each port a pin is an input or output. ddra is not in the address map during expanded and peripheral mode operation. setting a bit in ddra makes table 1-4. port description summary port name pin numbers data direction dd register (address) description port a pa 7 ? pa 0 46?39 in/out ddra ($0002) port a and port b pins are used for address and data in expanded modes. the port data registers are not in the address map during expanded and peripheral mode operation. when in the map, port a and port b can be read or written anytime. ddra and ddrb are not in the address map in expanded or peripheral modes. port b pb7?pb0 25?18 in/out ddrb ($0003) port ad pa d 7 ? pa d 0 58?51 in analog-to-digital converter and general-purpose i/o port dlc/pcan (1) pdlc6?pdlc0 pcan6?pcan2 1. port dlc applies to the mc68hc912b32 and mc68hc12be32 and pcan to the mc68hc(9)12bc32. 70?76 in/out ddrdlc ($00ff) byte data link communica tion (bdlc) subsystem and general-purpose i/o port e pe7?pe0 26?29, 35?38 pe1?pe0 in pe7?pe2 in/out ddre ($0009) mode selection, bus control signals, and interrupt service request signals; or general-purpose i/o port p pp7?pp0 79, 80, 1?6 in/out ddrp ($0057) general-purpose i/o. pp3?pp0 are used with the pulse-width modulator when enabled. port s ps7?ps0 68?61 in/out ddrs ($00d7) serial communications interface and serial peripheral interface subsystems and general-purpose i/o port t pt7?pt0 16?12, 9?7 in/out ddrt ($00af) general-purpose i/o when not enabled for input capture and output compare in the timer and pulse accumulator subsystem
pinout and signal descriptions m68hc12b family data sheet, rev. 9.1 freescale semiconductor 33 the corresponding bit in port a an output; clearing a bit in ddra makes the corresponding bit in port a an input. the default reset state of ddra is all 0s. when the pupa bit in the pucr register is set, all port a input pins are pulled up internally by an active pullup device. this bit has no effect if the port is being used in expanded m odes as the pullups are inactive. setting the rdpa bit in the reduced drive register ( rdriv) causes all port a outputs to have reduced drive levels. rdriv can be written once after reset and is no t in the address map in peripheral mode. refer to chapter 6 bus control and input/output (i/o) . 1.6.4.2 port b port b pins are used for address and data in expanded m odes. the port data register is not in the address map during expanded and peripheral mode operation. when it is in the map, port b can be read or written at anytime. the port b data direction register (ddrb) determines wh ether each port b pin is an input or output. ddrb is not in the address map during expanded and peripheral mode operation. setting a bit in ddrb makes the corresponding bit in port b an output; clearing a bit in ddrb makes the corresponding bit in port b an input. the default reset state of ddrb is all 0s. when the pupb bit in the pucr register is set, all port b input pins are pulled up internally by an active pullup device. this bit has no effect if the port is being used in expanded modes because the pullups are inactive. setting the rdpb bit in register rdriv causes all por t b outputs to have reduced drive levels. rdriv can be written once after reset. rdri v is not in the address map in peripheral mode. refer to chapter 6 bus control and input/output (i/o) . 1.6.4.3 port e port e pins operate differently from port a and b pins. port e pins are used for bus control signals and interrupt service request signals. when a pin is not used for one of these specific functions, it can be used as general-purpose i/o. however, two of the pins, pe1 and pe0, can be used only for input, and the states of these pins can be read in the port data register even when they are used for irq and xirq . the pear register determines pin function, and the da ta direction register (ddre) determines whether each pin is an input or output when it is used for general-purpose i/o. pear settings override ddre settings. because pe1 and pe0 are input-only pins, on ly ddre7?ddre2 have effect. setting a bit in the ddre register makes the corresponding bit in port e an output; clearing a bit in the ddre register makes the corresponding bit in port e an input. the default reset state of ddre is all 0s. when the pupe bit in the pucr register is set, pe7, pe3, pe2, and pe0 are pulled up. pe7, pe3, pe2, and pe0 are active pulled-up devices, while pe1 is al ways pulled up by means of an internal resistor. port e and ddre are not in the map in peripheral mode or in expanded modes when the eme bit in the mode register is set. setting the rdpe bit in register rdriv causes all port e outputs to have reduced drive level. rdriv can be written once after reset. rdri v is not in the address map in peripheral mode. refer to chapter 6 bus control and input/output (i/o) .
general description m68hc12b family data sheet, rev. 9.1 34 freescale semiconductor 1.6.4.4 port dlc the mc68hc912b32 and mc68hc12be32 contain the port dlc. byte data link communications (bdlc) pins can be configured as general-purpose i/o port dlc. when bdlc functions are not enabled, the port has seven general-purpose i/o pins, pdlc6?pdlc0. the port dlc control register (dlcscr) controls port dlc function. the bdlc function, enabled with the bdlcen bit, takes precedence over other port functions. the port dlc data direction register (ddrdlc) determines whether each port dlc pin is an input or output. setting a bit in ddrdlc makes the corresponding pin in port dlc an output; clearing a bit makes the corresponding pin an input. after reset, port dlc pins are configured as inputs. when the pupdlc bit in the dlcscr register is set, all port dlc input pins are pulled up internally by an active pullup device. setting the rdpdlc bit in register dlcscr causes all port dlc outputs to have reduced drive level. levels are at normal drive capability after reset. rdpdlc can be written anytime after reset. refer to chapter 15 byte data link communications (bdlc) . 1.6.4.5 port can the mc68hc(9)12bc32 contains the port can. the port can has five general-purpose i/o pins, pc an[6:2]. the mscan12 receive pin, rxcan, and transmit pin, txcan, cannot be config ured as general-purpose i/o on port can. the mscan data direction register (ddrcan) det ermines whether each port can pin pcan[6:2] is an input or output. setting a bit in ddrcan makes the co rresponding pin in port can an output; clearing a bit makes the corresponding pin an input. after reset, port can pins pcan[6:2] are configured as inputs. when a read to the port can is performed, the value read from the most significant bit (msb) depends on the msb, pcan7, of the port can data regist er, portcan, and the msb of ddrcan: it is 0 if ddrcan7 = 0 and is pcan7 if ddrcan7 = 1. when the peucan bit in the port can control register (pctlcan) is set, port can input pins pcan[6:2] are pulled up internally by an active pullup device. setting the rdrcan bit in register pctlcan causes the port can outputs pcan[6:2} to have reduced drive level. levels are at normal dr ive capability after reset. rdrcan c an be written anytime after reset. refer to chapter 16 mscan12 controller . 1.6.4.6 port ad port ad provides input to the analog-to-digital subsystem and general-purpose input. when analog-to-digital functions are not enabled, the port has eight general-purpose input pins, pad7?pad0. the adpu bit in the atd control register 2 (atdctl2) enables the a/d function. port ad pins are inputs; no data direction register is associated with this port. the port has no resistive input loads and no reduced drive controls. refer to chapter 17 analog-to-digital converter (atd) .
pinout and signal descriptions m68hc12b family data sheet, rev. 9.1 freescale semiconductor 35 1.6.4.7 port p the four pulse-width modulation channel outputs share general-purpose port p pins. the pwm function is enabled with the pwm enable register (pwen). enabling pwm pins takes precedence over the general-purpose port. when pulse-width modulation is not in use, the port pins may be used for general-purpose i/o. the port p data direction register (ddrp) dete rmines pin direction of port p when used for general-purpose i/o. when ddrp bits are set, the corre sponding pin is configured for output. on reset, the ddrp bits are cleared and the corresponding pin is configured for input. when the pupp bit in the pwm control register (pwc tl) register is set, all input pins are pulled up internally by an active pullup device. pullups are disabled after reset. setting the rdpp bit in the pwctl register configures all port p outputs to have reduced drive levels. levels are at normal drive capability after reset. the pwctl register can be read or written anytime after reset. refer to chapter 11 pulse-width modulator (pwm) . 1.6.4.8 port t this port provides eight general-purpose i/o pins when not enabled for input capture and output compare in the timer and pulse accumulator subsystem. the ten bit in the timer system control register (tscr) enables the timer function. the pulse accumulator subsystem is enabled with the paen bit in the pulse accumulator control register (pactl). the port t data direction register (ddrt) determines pin direction of port t when used for general-purpose i/o. when ddrt bits are set, the co rresponding pin is configured for output. on reset the ddrt bits are cleared and the corresponding pin is configured for input. when the pupt bit in the timer mask register 2 (tmsk2) is set, all input pins are pulled up internally by an active pullup device. pull ups are disabled after reset. setting the rdpt bit in the tmsk2 register configur es all port t outputs to have reduced drive levels. levels are at normal drive capability after reset. the tmsk2 register can be read or written anytime after reset. for the mc68hc912b32 and mc68hc(9)12bc32, refer to chapter 12 standard timer (tim) . for the mc68hc12be32, refer to chapter 13 enhanced capture timer (ect) module . 1.6.4.9 port s port s is the 8-bit interface to the standard serial interface consisting of the serial communications interface (sci) and serial peripheral interface ( spi) subsystems. port s pins are available for general-purpose parallel i/o when standard serial functions are not enabled. port s pins serve several functions depending on the vari ous internal control registers. if woms bit in the sci control register 1 (sc0cr1) is set, the p-channel drivers of the output buffers are disabled for bits 0?1 (2?3). if swom bit in the sp0cr1 register is set, the p-channel drivers of the output buffers are disabled for bits 4?7 (wired-or mode). the open drain control affects both the serial and the general-purpose outputs. if the rdpsx bits in the purd s register are set, the appropriate port s pin drive capabilities are reduced. if pupsx bits in the port s pullup, reduced drive register (purds) are set, the appropriate pullup device is connected to each port s pin which is programmed as a general-purpose input. if the pin is programmed as a general-purpose output, the pul lup is disconnected from the pin regardless of the state of the individual pupsx bits.
general description m68hc12b family data sheet, rev. 9.1 36 freescale semiconductor 1.6.5 port pullup, pu lldown, and reduced drive mcu ports can be configured for internal pullup. to reduce power consumption and rfi, the pin output drivers can be configured to operate at a reduced drive level. reduced drive causes a slight increase in transition time depending on loading and should be used only for ports which have a light loading. table 1-5 summarizes the port pullup default status and controls. table 1-5. port pullup, pulldown, and reduced drive summary port name resistive input loads enable bit reduced drive control bit register (address) bit name reset state register (address) bit name reset state port a pullup pucr ($000c) pupa disabled rdriv ($000d) rdpa full drive port b pullup pucr ($000c) pupb disabled rdriv ($000d) rdpb full drive port e pe7, pe3, pe2, pe1, pe0 pullup pucr ($000c) pupe enabled rdriv ($000d) rdpe full drive port e pe4 none ? rdriv ($000d) rdpe full drive port e pe6, pe5 pulldown enabled during reset ? ? ? port p pullup pwctl ($0054) pupp disabled pwctl ($0054) rdpp full drive port s ps1?ps0 pullup purds ($00db) pups0 disabled purds ($00db) rdps0 full drive port s ps3?ps2 pullup purds ($00db) pups1 disabled purds ($00db) rdps1 full drive port s ps7?ps4 pullup purds ($00db) pups2 disabled purds ($00db) rdps2 full drive port t pullup tmsk2 ($008d) pupt disabled tmsk2 ($008d) rdpt full drive port dlc/pcan (1) 1. port dlc applies to the mc68hc912b32 and mc68hc12be32 and pcan to the mc68hc(9)12bc32. pullup dlcscr ($00fd) dlcpue disabled dlcscr ($00fd) dlcrdv full drive port ad none ? ? bkgd pullup ? ? enabled ? ? full drive
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 37 pinout and signal descriptions figure 1-8. basic single-chip mode schematic 10 47 78 31 59 11 48 77 30 49 50 69 33 34 32 17 38 37 36 35 29 28 27 26 v dd0 v dd1 v ddx0 v ddx1 v ddad v ss0 v ss1 v ssx0 v ssx1 18 19 20 21 22 23 24 25 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 39 40 41 42 43 44 45 46 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 61 62 63 64 65 66 67 68 ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 51 52 53 54 55 56 57 58 pad0 pad1 pad2 pad3 pad4 pad5 pad6 pad7 7 8 9 12 13 14 15 16 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 6 5 4 3 2 1 80 79 76 75 74 73 72 71 pp0 pp1 pp2 pp3 pp4 pp5 pp6 pp7 v rh v rl v fp extal xtal reset bkgd pe0 pe1 pe2/r/w pe3/lstrb pe4/eclock pe5/moda pe6/modb pe7/dbe pdlc0 pdlc1 pdlc2 pdlc3 pdlc4 pdlc5 v dd0 v dd1 v ddx1 v ddx0 v ddad c2 c1 y1 jp1 1 2 3 4 5 6 gnd v dd 1 2 3 4 5 6 mc68hc912b32 header 6 u1 reset moda modb r29 r31 r34 r36 r38 r40 r42 r44 r46 r48 r50 r52 r54 r56 r57 r58 v ddex0 4 3 moda modb sw dip-2 1 2 s1 v dd v dd r2 4.7 k r3 4.7 k r14 r32 4.7 k v dd1 c6 1.0 f c5 1.0 f c4 1.0 f v ddex0 v ddad c3 1.0 f v dd0 ground v fp dn in rset 21 3 u2 mc34064 reset v fp 70 pdlc6 v dd note: this figure provides a suggested schematic only.
m68hc12b family data sheet, rev. 9.1 38 freescale semiconductor general description figure 1-9. ram expansion schematic with flash in narrow mode 6 e clock a15 10 47 78 31 59 11 48 77 30 49 50 69 33 34 32 17 38 37 36 35 29 28 27 26 v dd0 v dd1 v ddx0 v ddx1 v ddad v ss0 v ss1 v ssx0 v ssx1 18 19 20 21 22 23 24 25 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 39 40 41 42 43 44 45 46 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 61 62 63 64 65 66 67 68 ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 51 52 53 54 55 56 57 58 pad0 pad1 pad2 pad3 pad4 pad5 pad6 pad7 7 8 9 12 13 14 15 16 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 6 5 4 3 2 1 80 79 76 75 74 73 72 71 pp0 pp1 pp2 pp3 pp4 pp5 pp6 pp7 v rh v rl v fp extal xtal reset bkgd pe0 pe1 pe2/r/w pe3/lstrb pe4/eclock pe5/moda pe6/modb pe7/dbe pdlc0 pdlc1 pdlc2 pdlc3 pdlc4 pdlc5 dn in rset 21 3 u1 mc34064 reset v dd v dd v ddx1 v ddx0 v dd ground r1 c2 c1 y1 jp1 1 2 3 4 5 6 gnd v dd 1 2 3 4 5 6 e clock mc68hc912b32 header 6 d0 d1 d2 d3 d4 d5 d7 3 4 7 8 13 14 17 18 d6 d0 d1 d2 d3 d4 d5 d6 d7 u3 oc clk 74hc374 1 11 e clock q0 q1 q2 q3 q4 q5 q6 q7 2 5 6 9 12 15 16 19 a15 a14 a13 a12 a11 a10 a9 a8 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 11 12 13 14 15 16 17 18 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 ce r/w oe ram ic 20 27 22 u4 u2 reset v fp moda modb r/w 1 2 3 4 5 a b c g1 g2a g2b u6 74ahct138 y0 y1 y2 y3 y4 y5 y6 y7 15 14 13 12 11 10 9 7 ram flash a13 a14 a15 ram r/w a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 13 14 15 17 18 19 20 21 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 ce oe 22 24 31 u4 flash ground a15 a16 3 2 1 pgm v pp flash v dd am27c010 r62 10 k v dd1 c10 0.1 f c9 0.1 f c8 0.1 f v ddx0 v ddx1 v fp 70 pdlc6 d0 d1 d2 d3 d4 d5 d7 d6 4 3 moda modb sw dip-2 1 2 s1 v dd v dd r2 4.7 k r3 4.7 k r32 4.7 k note: this figure provides a suggested schematic only.
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 39 chapter 2 register block 2.1 introduction the register block can be mapped to any 2-kbyte boundary within the standard 64-kbyte address space by manipulating bits reg15?reg11 in the register in itialization register (initrg). initrg establishes the upper five bits of the register block?s 16-bit addr ess. the register block occupies the first 512 bytes of the 2-kbyte block. default addressing (after reset) is indicated in figure 2-1 . for additional information, refer to chapter 5 operating modes and resource mapping . note in expanded and peripheral modes, thes e registers are not in the map: port a data register, porta port b data register, portb port a data direction register, ddra port b data direction register, ddrb in peripheral mode or in expanded modes w ith the emulate port e bit (eme) set, these registers are not in the map: port e data register, porte port e data direction register, ddre in peripheral mode, these registers are not in the map: mode register, mode pullup control register, pucr reduced drive register, rdriv
register block m68hc12b family data sheet, rev. 9.1 40 freescale semiconductor 2.2 registers addr. register name bit 7654321bit 0 $0000 port a data register (porta) see page 86. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset:uuuuuuuu $0001 port b data register (portb) see page 87. read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset:uuuuuuuu $0002 data direction register a (ddra) see page 86. read: dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 write: reset:00000000 $0003 data direction register b (ddrb) see page 87. read: ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 write: reset:00000000 $0004 reserved r r r r r r r r $0007 reserved r r r r r r r r $0008 port e data register (porte) see page 88. read: pe7 pe6 pe5 pd4 pd3 pd2 pd1 pd0 write: reset:00000000 $0009 data direction register e (ddre) see page 88. read: dde7 dde6 dde5 dde4 dde3 dde2 00 write: reset:00001000 $000a port e assignment register (pear) see page 89. read: ndbe cgmte pipoe neclk lstre rdwe 00 write: reset:10010000 $000b mode register (mode) see page 78. read: smodn modb moda estr ivis ebswai 0 eme write: reset:00011001 $000c pullup control register (pucr) see page 91. read: 0 0 0 pupe 00 pupb pupa write: reset:00010000 $000d reduced drive register (rdriv) see page 92. read:0000 rdpe 0 rdpb rdpa write: reset:00000000 $000e reserved r r r r r r r r $000f reserved r r r r r r r r = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 1 of 19)
registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 41 $0010 ram initialization register (initrm) see page 80. read: ram15ram14ram13ram12ram11 0 0 0 write: reset:00001000 $0011 register initialization register (initrg) see page 80. read: reg15 reg14 reg13 reg12 reg11 0 0 mmswai write: reset:00000000 $0012 eeprom initialization register (initee) see page 81. read: ee15 ee14 ee13 ee12 0 0 0 eeon write: reset:00010001 $0013 miscellaneous mapping control register (misc) see page 82. read: 0 ndrf rfstr1 rfstr0 exstr1 exstr0 maprom romon write: reset:00000000 $0014 real-time interrupt control register (rtictl) see page 118. read: rtie rswai rsbck 0 rtbyp rtr2 rtr1 rtr0 write: reset:00000000 $0015 real-time interrupt flag register (rtiflg) see page 119. read: rtif0000000 write: reset:00000000 $0016 cop control register (copctl) see page 119. read: cme fcme fcm fcop disr cr2 cr1 cr0 write: reset:00000001 $0017 arm/reset cop timer register (coprst) see page 120. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0018 reserved r r r r r r r r $001d reserved r r r r r r r r $001e interrupt control register (intcr) see page 70. read: irqeirqendly00000 write: reset:01100000 $001f highest priority i interrupt register (hprio) see page 71. read: 1 1 psel5 psel4 psel3 psel2 psel1 0 write: reset:11110010 $0020 breakpoint control register 0 (brkct0) see page 301. read: bken1 bken0 bkpm 0 bk1ale bk0ale 0 0 write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 2 of 19)
register block m68hc12b family data sheet, rev. 9.1 42 freescale semiconductor $0021 breakpoint control register 1 (brkct1) see page 302. read: 0 bkdbe bkmbh bkmbl bk1rwe bk1rw bk0rwe bk0rw write: reset:00000000 $0022 breakpoint address register high (brkah) see page 303. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0023 breakpoint address register low (brkal) see page 303. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 $0024 breakpoint data register high (brkdh) see page 304. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0025 breakpoint data register low (brkdl) see page 304. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0026 reserved r r r r r r r r $003f reserved r r r r r r r r $0040 pwm clocks and concatenate register (pwclk) see page 128. read: con23 con01 pcka2 pcka1 pcka0 pckb2 pckb1 pckb0 write: reset:00000000 $0041 pwm clock select and polarity register (pwpol) see page 129. read: pclk3 pclk2 pclk1 pclk0 ppol3 ppol2 ppol1 ppol0 write: reset:00000000 $0042 pwm enable register (pwen) see page 130. read:0000 pwen3 pwen2 pwen1 pwen0 write: reset:00000000 $0043 pwm prescaler counter register (pwpres) see page 131. read: 0 bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0044 pwm scale register 0 (pwscal0) see page 131. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0045 pwm scale counter register 0 (pwscnt0) see page 131. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 3 of 19)
registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 43 $0046 pwm scale register 1 (pwscal1) see page 132. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0047 pwm scale counter register 1 (pwscnt1) see page 132. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0048 pwm channel counter register 0 (pwcnt0) see page 133. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0049 pwm channel counter register 1 (pwcnt1) see page 133. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $004a pwm channel counter register 2 (pwcnt2) see page 133. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $004b pwm channel counter register 3 (pwcnt3) see page 133. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $004c pwm channel period register 0 (pwper0) see page 134. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $004d pwm channel period register 1 (pwper1) see page 134. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $004e pwm channel period register 2 (pwper2) see page 134. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $004f pwm channel period register 3 (pwper3) see page 134. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $0050 pwm channel duty register 0 (pwdty0) see page 135. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $0051 pwm channel duty register 1 (pwdty1) see page 135. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 4 of 19)
register block m68hc12b family data sheet, rev. 9.1 44 freescale semiconductor $0052 pwm channel duty register 2 (pwdty2) see page 135. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $0053 pwm channel duty register 3 (pwdty3) see page 135. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $0054 pwm control register (pwctl) see page 136. read: 0 0 0 pswai centr rdpp pupp psbck write: reset:00000000 $0055 pwm special mode register (pwtst) see page 137. read: discr discp discal 00000 write: reset:00000000 $0056 port p data register (portp) see page 137. read: pp7 pp6 pp5 pp4 pp3 pp2 pp1 pp0 write: reset:uuuuuuuu $0057 port p data direction register (ddrp) see page 138. read: ddp7 ddp6 ddp5 ddp4 ddp3 ddp2 ddp1 ddp0 write: reset:00000000 $0058 reserved r r r r r r r r $005f reserved r r r r r r r r $0060 atd control register 0 (atdctl0) see page 279. read: 00000000 write: reset:00000000 $0061 atd control register 1 (atdctl1) see page 279. read: 00000000 write: reset:00000000 $0062 atd control register 2 (atdctl2) see page 279. read: adpu affc awai 000 ascie ascif write: reset:00000000 $0063 atd control register 3 (atdctl3) see page 280. read:000000 frz1 frz0 write: reset:00000000 $0064 atd control register 4 (atdctl4) see page 281. read: s10bmsmp1smp0prs4prs3prs2prs1prs0 write: reset:00000001 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 5 of 19)
registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 45 $0065 atd control register 5 (atdctl5) see page 282. read: s8cm scan mult cd cc cb ca write: reset:00000000 $0066 atd status register (atdstat) see page 284. read: scf 0 0 0 0 cc2 cc1 cc0 write: reset:00000000 $0067 atd status register (atdstat) see page 284. read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: reset:00000000 $0068 atd test register high (atdtsth) see page 285. read: sar9 sar8 sar7 sar6 sar5 sar4 sar3 sar2 write: reset:00000000 $0069 atd test register low (atdtstl) see page 285. read: sar1 sar0 rst tstout tst3 tst2 tst1 tst0 write: reset:00000000 $006a reserved r r r r r r r r $006e reserved r r r r r r r r $006f port ad data input register (portad) see page 286. read: pad7 pad6 pad5 pad4 pad3 pad2 pad1 pad0 write: reset: after reset, reflect the state of the input pins $0070 atd result register 0 (adrx0h) see page 286. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: undefined $0071 atd result register 0 (adrx0l) see page 286. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: undefined $0072 atd result register 1 (adrx1h) see page 286. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: undefined $0073 atd result register 1 (adrx1l) see page 286. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: undefined $0074 atd result register 2 (adrx2h) see page 286. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: undefined addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 6 of 19)
register block m68hc12b family data sheet, rev. 9.1 46 freescale semiconductor $0075 atd result register 2 (adrx2l) see page 286. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: undefined $0076 atd result register 3 (adrx3h) see page 286. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: undefined $0077 atd result register 3 (adrx3l) see page 286. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: undefined $0078 atd result register 4 (adrx4h) see page 286. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: undefined $0079 atd result register 4 (adrx4l) see page 286. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: undefined $007a atd result register 5 (adrx5h) see page 286. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: undefined $007b atd result register 5 (adrx5l) see page 286. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: undefined $007c atd result register 6 (adrx6h) see page 286. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: undefined $007d atd result register 6 (adrx6l) see page 286. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: undefined $007e atd result register 7 (adrx7h) see page 286. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: undefined $007f atd result register 7 (adrx7l) see page 286. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: undefined $0080 timer ic/oc select register (tios) see page 141. read: ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 7 of 19)
registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 47 $0081 timer compare force register (cforc) see page 141. read: foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 write: reset:00000000 $0082 timer output compare 7 mask register (oc7m) see page 143. read: oc7m7oc7m6oc7m5oc7m4oc7m3oc7m2oc7m1oc7m0 write: reset:00000000 $0083 timer output compare 7 data register (oc7d) see page 143. read: oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 write: reset:00000000 $0084 timer count register high (tcnth) see page 144. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0085 timer count register low (tcntl) see page 144. read:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0086 timer system control register (tscr) see page 144. read: ten tswai tsbck tffca write: reset:00000000 $0087 reserved r r r r r r r r $0088 timer control register 1 (tctl1) see page 145. read: om7 ol7 om6 ol6 om5 ol5 om4 ol4 write: reset:00000000 $0089 timer control register 2 (tctl2) see page 145. read: om3 ol3 om2 ol2 om1 ol1 om0 ol0 write: reset:00000000 $008a timer control register 3 (tctl3) see page 146. read: edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a write: reset:00000000 $008b timer control register 4 (tctl4) see page 146. read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a write: reset:00000000 $008c timer mask register 1 (tmsk1) see page 146. read: c7i c6i c5i c4i c3i c2i c1i c0i write: reset:00000000 $008d timer mask register 2 (tmsk2) see page 147. read: toi 0 pupt rdpt tcre pr2 pr1 pr0 write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 8 of 19)
register block m68hc12b family data sheet, rev. 9.1 48 freescale semiconductor $008e timer interrupt flag register 1 (tflg1) see page 148. read: c7f c6f c5f c4f c3f c2f c1f c0f write: reset:00000000 $008f timer interrupt flag register 2 (tflg2) see page 148. read: tof0000000 write: reset:00000000 $0090 timer input capture/output compare 0 register high (tc0h) see page 149. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0091 timer input capture/output compare 0 register low (tc0l) see page 149. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0092 timer input capture/output compare 1 register high (tc1h) see page 149. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0093 timer input capture/output compare 1 register low (tc1l) see page 149. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0094 timer input capture/output compare 2 register high (tc2h) see page 150. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0095 timer input capture/output compare 2 register low (tc2l) see page 150. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0096 timer input capture/output compare 3 register high (tc3h) see page 150. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0097 timer input capture/output compare 3 register low (tc3l) see page 150. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0098 timer input capture/output compare 4 register high (tc4h) see page 150. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0099 timer input capture/output compare 4 register low (tc4l) see page 150. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 9 of 19)
registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 49 $009a timer input capture/output compare 5 register high (tc5h) see page 150. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $009b timer input capture/output compare 5 register low (tc5l) see page 150. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $009c timer input capture/output compare 6 register high (tc6h) see page 151. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $009d timer input capture/output compare 6 register low (tc6l) see page 151. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $009e timer input capture/output compare 7 register high (tc7h) see page 151. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $009f timer input capture/output compare 7 register low (tc7l) see page 151. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00a0 pulse accumulator control register (pactl) see page 151. read: 0 paen pamod pedge clk1 clk0 paovi pai write: reset:00000000 $00a1 pulse accumulator flag register (paflg) see page 153. read: 0 0 0 0 0 0 paovf paif write: reset:00000000 $00a2 pulse accumulator count register 3 (pacn3) see page 178. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00a3 pulse accumulator count register 2 (pacn2) see page 178. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00a4 pulse accumulator count register 1 (pacn1) see page 178. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00a5 pulse accumulator count register 0 (pacn0) see page 178. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 10 of 19)
register block m68hc12b family data sheet, rev. 9.1 50 freescale semiconductor $00a6 16-bit modulus down-counter control register (mcctl) see page 179. read: mczi modmc rdmcl iclat flmc mcen mcpr1 mcpr0 write: reset:00000000 $00a7 16-bit modulus down-counter flag register (mcflg) see page 180. read: mczf 0 0 0 polf3 polf2 polf1 polf0 write: reset:00000000 $00a8 input control pulse accumulators control register (icpacr) see page 181. read: 0 0 0 0 pa3en pa2en pa1en pa0en write: reset:00000000 $00a9 delay counter control register (dlyct) see page 181. read: 000000dly1dly0 write: reset:00000000 $00aa input control overwrite register (icovw) see page 182. read: novw7 novw6 novw5 novw4 novw3 novw2 novw1 novw0 write: reset:00000000 $00ab input control system control register (icsys) see page 182. read: sh37 sh26 sh15 hs04 tfmod pacmx bufen latq write: reset:00000000 $00ac reserved r r r r r r r r $00ad timer test register (timtst) see page 183. read: 0 0 0 0 0 0 tcbyp pcbyp (1) write: reset:00000000 $00ae timer port data register (portt) see page 184. read: pt7 pt6 pt5 pt4 pt3 pt2 pt1 pt0 write: reset:00000000 $00af data direction register for timer port (ddrt) see page 184. read: ddt7 ddt6 ddt5 ddt4 ddt3 ddt2 ddt1 ddt0 write: reset:00000000 $00b0 16-bit pulse accumulator b control register (pbctl) see page 185. read: 0 pben 0 0 0 0 pbov 0 write: reset:00000000 $00b1 pulse accumulator b flag register (pbflg) see page 185. read: 000000pbov0 write: reset:00000000 $00b2 8-bit pulse accumulator holding register 3 (pa3h) see page 186. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 11 of 19)
registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 51 $00b3 8-bit pulse accumulator holding register 2 (pa2h) see page 186. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00b4 8-bit pulse accumulator holding register 1 (pa1h) see page 186. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00b5 8-bit pulse accumulator holding register 0 (pa0h) see page 186. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00b6 modulus down-counter count register (mccnt) see page 187. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 $00b7 modulus down-counter count register (mccnt) see page 187. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 $00b8 timer input capture holding register 0 (tc0h) see page 187. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00100000 $00b9 timer input capture holding register 0 (tc0h) see page 188. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00ba timer input capture holding register 1 (tc1h) see page 188. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $00bb timer input capture holding register 1 (tc1h) see page 188. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00bc timer input capture holding register 2 (tc2h) see page 188. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $00bd timer input capture holding register 2 (tc2h) see page 188. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00be timer input capture holding register 3 (tc3h) see page 188. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 12 of 19)
register block m68hc12b family data sheet, rev. 9.1 52 freescale semiconductor $00bf timer input capture holding register 3 (tc3h) see page 188. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00c0 sci 0 baud rate control register high (sc0bdh) see page 194. read: btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 write: reset:00000000 $00c1 sci 0 baud rate control register low (sc0bdl) see page 194. read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: reset:00000100 $00c2 sci control register 1 (sc0cr1) see page 195. read: loops woms rsrc m wake ilt pe pt write: reset:00000000 $00c3 sci control register 2 (sc0cr2) see page 197. read: tie tcie rie ilie te re rwu sbk write: reset:00000000 $00c4 sci status register 1 (sc0sr1) see page 198. read: tdre tc rdrf idle or nf fe pf write: reset:11000000 $00c5 sci status register 2 (sc0sr2) see page 199. read:0000000raf write: reset:00000000 $00c6 sci data register high (sc0drh) see page 200. read: r8 t8000000 write: reset:uu000000 $00c7 sci data register low (sc0drl) see page 200. read: r7t7 r6t6 r5t5 r4t4 r3t3 r2t2 r1t1 r0t0 write: reset: unaffected by reset $00c8 reserved r r r r r r r r $00cf reserved r r r r r r r r $00d0 spi control register 1 (sp0cr1) see page 204. read: spie spe swom mstr cpol cpha ssoe lsbf write: reset:00000000 $00d1 spi control register 2 (sp0cr2) see page 205. read:0000 pups rds 0 spc0 write: reset:00001000 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 13 of 19)
registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 53 $00d2 spi baud rate register (sp0br) see page 206. read:00000 spr2 spr1 spr0 write: reset:00000000 $00d3 spi status register (sp0sr) see page 207. read: spif wcol 0 modf 0 0 0 0 write: reset:00000000 $00d4 reserved r r r r r r r r $00d5 spi data register (sp0dr) see page 207. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset $00d6 port s data register (ports) see page 208. read: ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 write: reset: after reset all bits configured as general-purpose inputs $00d7 port s data direction register (ddrs) see page 208. read: dds7 dds6 dds5 dds4 dds3 dds2 dds1 dds0 write: reset: after reset all bits configured as general-purpose inputs $00d8 reserved r r r r r r r r $00da reserved r r r r r r r r $00db port s pullup/reduced drive register (purds) see page 209. read: 0 rdps2 rdps1 rdps0 0 pups2 pups1 pups0 write: reset:00000000 $00dc reserved rrrrrrrr $00df reserved r r r r r r r r $00e0 slow mode divider register (slow) see page 117. read:00000 sldv2 sldv1 sldv0 write: reset:00000000 $00e1 reserved r r r r r r r r $00ef reserved r r r r r r r r $00f0 eeprom configuration register (eemcr) see page 94. read: 1 1 1 1 1 eeswai protlck eerc write: reset:11111100 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 14 of 19)
register block m68hc12b family data sheet, rev. 9.1 54 freescale semiconductor $00f1 eeprom block protect register (eeprot) see page 95. read: 1 1 1 brprot4 brprot3 brprot2 brprot1 brprot0 write: reset:11111111 $00f2 eeprom test register (eetst) see page 95. read: eeodd eeven marg eecpd eecprd 0 eecpm 0 write: reset:00000000 $00f3 eeprom control register (eeprog) see page 96. read: bulkp 0 0 byte row erase eelat eepgm write: reset:10000000 $00f4 flash eeprom lock control register (feelck) (1) see page 100. read: 0000000lock write: reset:00000000 $00f5 flash eeprom configuration register (feemcr) (1) see page 100. read: 0000000bootp write: reset:00000001 $00f6 flash eeprom test register (feetst) (1) see page 100. read: fste gadr hvt fenlv fdisvfp vtck stre mwpr write: reset:00000000 $00f7 flash eeprom control register (feectl) (1) see page 102. read: 0 0 0 feeswai svfp eras lat enpe write: reset:00000000 $00f8 bdlc control register 1 (bcr1) (2) see page 231. read: imsg clks r1 r0 00 ie wcm write: r r reset:11100000 $00f9 bdlc state vector register (bsvr) (2) see page 237. read: 0 0 i3 i2 i1 i0 0 0 write: reset:00000000 $00fa bdlc control register 2 (bcr2) (2) see page 233. read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: reset:11000000 $00fb bdlc data register (bdr) (2) see page 239. read: bd7 bd6 bd5 bd4 bd3 bd2 bd1 bd0 write: reset: indeterminate after reset $00fc bdlc analog roundtrip delay register (bard) (2) see page 240. read: ate rxpol 00 bo3 bo2 bo1 bo0 write: reset:11000111 addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 15 of 19)
registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 55 $00fd port dlc control register (dlcscr) (2) see page 241. read:00000 bdlcen pupdlc rdpdlc write: reset:00000000 $00fe port dlc data register (portdlc) (2) see page 242. read: 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:0uuuuuuu $00ff port dlc data direction register (ddrdlc) (2) see page 242. read: 0 dddlc6 dddlc5 dddlc4 dddlc3 dddlc2 dddlc1 dddlc0 write: reset:00000000 $0100 mscan12 module control register 0 (cmcr0) (3) see page 262. read: 0 0 cswai synch tlnken slpak slprq sftres write: reset:00100001 $0101 mscan12 module control register 1 (cmcr1) (3) see page 263. read:00000 loopb wupm clksrc write: reset:00000000 $0102 mscan12 bus timing register 0 (cbtr0) (3) see page 264. read: sjw1 sjw0 brp5 brp4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 $0103 mscan12 bus timing register 1 (cbtr1) (3) see page 265. read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: reset:00000000 $0104 mscan12 receiver flag register (crflg) (3) see page 266. read: wupif rwrnif twrnif rerrif terrif boffif ovrif rxf write: reset:00000000 $0105 mscan12 receiver interrupt enable register (crier) (3) see page 268. read: wupie rwrnie twrnie rerrie terrie boffie ovrie rxfie write: reset:00000000 $0106 mscan12 transmitter flag register (ctflg) (3) see page 269. read: 0 abtak2 abtak1 abtak0 0 txe2 txe1 txe0 write: reset:00000111 $0107 mscan12 transmitter control register (ctcr) (3) see page 270. read: 0 abtrq2 abtrq1 abtrq0 0 txeie2 txeie1 txeie0 write: reset:00000000 $0108 mscan12 identifier acceptance control register (cidac) (3) see page 270. read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: reset:00000000 $0109 reserved r r r r r r r r addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 16 of 19)
register block m68hc12b family data sheet, rev. 9.1 56 freescale semiconductor $010d reserved r r r r r r r r $010e mscan12 receive error counter (crxerr) (3) see page 271. read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: reset:00000000 $010f mscan12 transmit error counter (ctxerr) (3) see page 272. read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: reset:00000000 $0110 mscan12 identifier acceptance register 0 (cidar0) (3) see page 272. read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset $0111 mscan12 identifier acceptance register 1 (cidar1) (3) see page 272. read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset $0112 mscan12 identifier acceptance register 2 (cidar2) (3) see page 272. read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset $0113 mscan12 identifier acceptance register 3 (cidar3) (3) see page 272. read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset $0114 mscan12 identifier mask register 0 (cidmr0) (3) see page 274. read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset $0115 mscan12 identifier mask register 1 (cidmr1) (3) see page 274. read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset $0116 mscan12 identifier mask register 2 (cidmr2) (3) see page 274. read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset $0117 mscan12 identifier mask register 3 (cidmr3) (3) see page 274. read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset $0118 mscan12 identifier acceptance register 4 (cidar4) (3) see page 273. read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset $0119 mscan12 identifier acceptance register 5 (cidar5) (3) see page 273. read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 17 of 19)
registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 57 $011a mscan12 identifier acceptance register 6 (cidar6) (3) see page 273. read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset $011b mscan12 identifier acceptance register 7 (cidar7) (3) see page 273. read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset $011c mscan12 identifier mask register 4 (cidmr4) (3) see page 274. read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset $011d mscan12 identifier mask register 5 (cidmr5) (3) see page 274. read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset $011e mscan12 identifier mask register 6 (cidmr6) (3) see page 274. read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset $011f mscan12 identifier mask register 7 (cidmr7) (3) see page 274. read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset $0120 reserved r r r r r r r r $013c reserved r r r r r r r r $013d mscan12 port can control register (pctlcan) (3) see page 275. read:000000 puecan rdpcan write: reset:00000000 $013e mscan12 port can data register (portcan) (3) see page 275. read: pcan7 pcan6 pcan5 pcan4 pcan2 pcan2 txcan rxcan write: reset: unaffected by reset $013f mscan12 port can data direction register (ddrcan) (3) see page 276. read: ddrcan7 ddrcan6 ddrcan5 ddrcan4 ddrcan3 ddrcan2 00 write: reset:00000000 $0140 $014f receive buffer (rxfg) (3) ? see 16.3.2 receive structures $0150 $015f transmit buffer 0 (tx0) (3) ? see 16.3.3 transmit structures addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 18 of 19)
register block m68hc12b family data sheet, rev. 9.1 58 freescale semiconductor $0160 $016f transmit buffer 1 (tx1) (3) ? see 16.3.3 transmit structures $0170 $017f transmit buffer 2 (tx2) (3) ? see 16.3.3 transmit structures addr. register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected notes: 1. available only on mc68hc912b32 and mc68hc912bc32 devices. 2. available only on mc68hc912b32 and mc68hc12be32 devices. 3. available only on mc68hc(9)12bc32 devices. figure 2-1. register map (sheet 19 of 19)
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 59 chapter 3 central processor unit (cpu) 3.1 introduction the cpu12 is a high-speed, 16-bit processor unit. it ha s full 16-bit data paths and wider internal registers (up to 20 bits) for high-speed extended math instructio ns. the instruction set is a proper superset of the m68hc11instruction set. the cpu12 allows instructions with odd byte counts, including many single-byte instructions. this provides efficient use of rom s pace. an instruction queue buffers program information so the cpu always has immediate access to at least three bytes of machine code at the start of every instruction. the cpu12 also offers an ext ensive set of indexed add ressing capabilities. 3.2 programming model cpu12 registers are an integral part of the cpu and are not addressed as if they were memory locations. see figure 3-1 . figure 3-1. programming model 7 15 15 15 15 15 d x y sp pc ab n sxh i zvc 0 0 0 0 0 0 7 0 condition code register 8-bit accumulators a and b 16-bit double accumulator d (a : b) index register x index register y stack pointer program counter stop disable (ignore stop opcodes) carry overflow zero negative irq interrupt mask (disable) half-carry for bcd arithmetic xirq interrupt mask (disable)
central processor unit (cpu) m68hc12b family data sheet, rev. 9.1 60 freescale semiconductor 3.3 cpu registers this section describes the cpu registers. 3.3.1 accumulators a and b accumulators a and b are general-purpose 8-bit accumulators that contain operands and results of arithmetic calculations or data manipulations. 3.3.2 accumulator d accumulator d is the concatenation of accumulators a and b. some instructions treat the combination of these two 8-bit accumulators as a 16-bit double accumulator. note the ldd and std instructions can be used to manipulate data in and out of accumulator d. bit 7654321bit 0 read: a7 a6 a5 a4 a3 a2 a1 a0 write: reset: unaffected by reset figure 3-2. accumulator a (a) bit 7654321bit 0 read: b7 b6 b5 b4 b3 b2 b1 b0 write: reset: unaffected by reset figure 3-3. accumulator b (b) figure 3-4. accumulator d (d) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: d15 (a7) d14 (a6) d13 (a5) d12 (a4) d11 (a3) d10 (a2) d9 (a1) d8 (a0) d7 (b7) d6 (b6) d5 (b5) d4 (b4) d3 (b3) d2 (b2) d1 (b1) d0 (b0) write: reset: unaffected by reset
cpu registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 61 3.3.3 index registers x and y index registers x and y are used for indexed addressing. indexed addressing adds the value in an index register to a constant or to the value in an accu mulator to form the effective address of the operand. index registers x and y can also serve as temporary data storage locations. note the ldx and stx instructions can be used to manipulate data in and out of index register x. note the ldy and sty instructions can be used to manipulate data in and out of index register y. 3.3.4 stack pointer the stack pointer (sp) contains the last stack address used. the cpu12 supports an automatic program stack that is used to save system context during subroutine calls and interrupts. the stack pointer can also serve as a temporary data storage location or as an index register for indexed addressing. note the lds and sts instructions can be used to manipulate data in and out of the stack pointer. figure 3-5. index register x (x) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 write: reset: unaffected by reset figure 3-6. index register y (y) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: y15 y14 y13 y12 y11 y10 y9 y8 y7 y6 y5 y4 y3 y2 y1 y0 write: reset: unaffected by reset figure 3-7. stack pointer (sp) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 write: reset: unaffected by reset
central processor unit (cpu) m68hc12b family data sheet, rev. 9.1 62 freescale semiconductor 3.3.5 program counter the program counter contains the addres s of the next instruction to be executed. the program counter can also serve as an index register in all indexed addressing modes except autoincrement and autodecrement. 3.3.6 condition code register s ? stop disable bit setting the s bit disables the stop instruction. x ? xirq interrupt mask bit setting the x bit masks interrupt requests from the xirq pin. h ? half-carry flag the h flag is used only for bcd arithmetic operati ons. it is set when an aba, add, or adc instruction produces a carry from bit 3 of accumulator a. the daa instruction uses the h flag and the c flag to adjust the result to the correct bcd format. i ? interrupt mask bit setting the i bit disables maskable interrupt sources. n ? negative flag the n flag is set when the result of an operation is less than 0. z ? zero flag the z flag is set when the result of an operation is all 0s. v ? two?s complement overflow flag the v flag is set when a two?s complement overflow occurs. c ? carry/borrow flag the c flag is set when an addition or subtraction operation produces a carry or borrow. figure 3-8. program counter (pc) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 write: reset: unaffected by reset bit 7654321bit 0 read: sxh i nzvc write: reset:1 1u1uuuu u = unaffected figure 3-9. condition code register (ccr)
data types m68hc12b family data sheet, rev. 9.1 freescale semiconductor 63 3.4 data types the cpu12 supports four data types: 1. bit data 2. 8-bit and 16-bit signed and unsigned integers 3. 16-bit unsigned fractions 4. 16-bit addresses a byte is eight bits wide and can be accessed at any byte location. a word is composed of two consecutive bytes with the most significant by te at the lower value address. there are no special requirements for alignment of instructions or operands. 3.5 addressing modes addressing modes determine how the cpu accesses memory locations to be operated upon. the cpu12 includes all of the addressing modes of the m68hc11 cpu as well as several new forms of indexed addressing. table 3-1 is a summary of the available addressing modes. table 3-1. addressing mode summary addressing mode source forma t abbreviation description inherent inst inh operands (if any) are in cpu registers. immediate inst # opr8i or inst # opr16i imm operand is included in instruction stream 8- or 16-bit size implied by context. direct inst opr8a dir operand is the lower 8 bits of an address in the range $0000?$00ff. extended inst opr16a ext operand is a 16-bit address. relative inst rel8 or inst rel16 rel an 8-bit or 16-bit relative offset from the current pc is supplied in the instruction. indexed 5-bit offset inst oprx5 , xysp idx 5-bit signed constant offset from x, y, sp, or pc indexed auto pre-decrement inst oprx3 , ?xys idx auto pre-decrement x, y, or sp by 1 ~ 8 indexed auto pre-increment inst oprx3 , +xys idx auto pre-increment x, y, or sp by 1 ~ 8 indexed auto post- decrement inst oprx3 , xys? idx auto post-decrement x, y, or sp by 1 ~ 8 indexed auto post-increment inst oprx3 , xys+ idx auto post-increment x, y, or sp by 1 ~ 8 indexed accumulator offset inst abd , xysp idx indexed with 8-bit (a or b) or 16-bit (d) accumulator offset from x, y, sp, or pc indexed 9-bit offset inst oprx9 , xysp idx1 9-bit signed constant offset from x, y, sp, or pc (lower 8 bits of offset in one extension byte) indexed 16-bit offset inst oprx16 , xysp idx2 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) table continued on next page
central processor unit (cpu) m68hc12b family data sheet, rev. 9.1 64 freescale semiconductor 3.6 indexed addressing modes the cpu12 indexed modes reduce execution time and e liminate code size penalties for using the y index register. cpu12 indexed addressing uses a postbyte pl us zero, one, or two extension bytes after the instruction opcode. the postbyte and extensions do these tasks: specify which index register is used determine whether a value in an accumulator is used as an offset enable automatic pre- or post-increment or decrement specify use of 5-bit, 9-bit, or 16-bit signed offsets indexed-indirect 16-bit offset inst [ oprx16 , xysp ][idx2] pointer to operand is found at 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) indexed-indirect d accumulator offset inst [d, xysp ][d,idx] pointer to operand is found at x, y, sp, or pc plus the value in d table 3-2. summary of indexed operations postbyte code (xb) source code syntax comments rr0nnnnn ,r n,r ?n,r 5-bit constant offset n = ?16 to +15 r can specify x, y, sp, or pc 111rr0zs n,r ?n,r constant offset (9- or 16-bit signed) z:0 = 9-bit with sign in lsb of postbyte(s) 1 = 16-bit if z = s = 1, 16-bit offset indexed-indirect (see below) rr can specify x, y, sp, or pc 111rr011 [n,r] 16-bit offset indexed-indirect rr can specify x, y, sp, or pc rr1pnnnn n,?r n,+r n,r? n,r+ auto pre-decrement/increment or auto post-decrement/increment ; p = pre-(0) or post-(1), n = ?8 to ?1, +1 to +8 rr can specify x, y, or sp (pc not a valid choice) 111rr1aa a,r b,r d,r accumulator offset (unsigned 8-bit or 16-bit) aa:00 = a 01 = b 10 = d (16-bit) 11 = see accumulator d offset indexed-indirect rr can specify x, y, sp, or pc 111rr111 [d,r] accumulator d offset indexed-indirect rr can specify x, y, sp, or pc rr: 00 = x, 01 = y, 10 = sp, 11 = pc table 3-1. addressing mode summary (continued) addressing mode source forma t abbreviation description
opcodes and operands m68hc12b family data sheet, rev. 9.1 freescale semiconductor 65 3.7 opcodes and operands the cpu12 uses 8-bit opcodes. each opcode identifies a particular instruction and associated addressing mode to the cpu. several opcodes are required to pr ovide each instruction with a range of addressing capabilities. only 256 opcodes would be available if the range of values were restricted to the number that can be represented by 8-bit binary numbers. to expand the number of opcodes, a second page is added to the opcode map. opcodes on the second page are preceded by an additional byte with the value $18. to provide additional addres sing flexibility, opcodes can also be followed by a postbyte or extension bytes. postbytes implement certain forms of i ndexed addressing, transfers, exchanges, and loop primitives. extension bytes contain additional program information such as addresses, offsets, and immediate data.
central processor unit (cpu) m68hc12b family data sheet, rev. 9.1 66 freescale semiconductor
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 67 chapter 4 resets and interrupts 4.1 introduction resets and interrupts are exceptions. each exception has a 16-bit vector that points to the memory location of the associated exception-handling routine. vectors are stored in the upper 128 bytes of the standard 64-kbyte address map. the six highest vector addresses are used for resets and non-maskable interrupt sources. the remainder of the vectors are used for maskable interrupts, and al l must be initialized to point to the address of the appropriate service routine. 4.2 exception priority a hardware priority hierarchy determines which reset or interrupt is serviced first when simultaneous requests are made. six sources are not maskable. the remaining sources are maskable, and any one of them can be given priority over other maskable interrupts. the priorities of the non-maskable sources are: 1. power-on reset (por) or reset pin 2. clock monitor reset 3. computer operating properly (cop) watchdog reset 4. unimplemented instruction trap 5. software interrupt instruction (swi) 6. xirq signal if x bit in ccr = 0 4.3 maskable interrupts maskable interrupt sources include on -chip peripheral system s and external interrupt service requests. interrupts from these sources are recognized when the global interrupt mask bit (i) in the condition code register (ccr) is cleared. the default state of the i bit out of reset is 1, but it c an be written at any time. interrupt sources are prioritized by default but any one maskable interrupt source may be assigned the highest priority by means of the hprio register. the re lative priorities of the other sources remain the same. an interrupt that is assigned highest priority is still subject to global masking by the i bit in the ccr or by any associated local bits. interrupt vectors are not affected by priority assignment. hprio can be written only while the i bit is set (interrupts inhibited). table 4-1 lists interrupt sources and vectors in default order of priority for all devices except the mc68hc(9)12bc32. table 4-2 lists the interrupt sources and vectors for the mc68hc(9)12bc32.
resets and interrupts m68hc12b family data sheet, rev. 9.1 68 freescale semiconductor table 4-1. interrupt vector map (1) 1. see table 4-2 for the mc68hc(9)12bc32 interrupt vector map. vector address interrupt source ccr mask local enable hprio value to elevate to highest i bit register bit(s) $fffe, $ffff reset none none none ? $fffc, $fffd cop clock monitor fail reset none copctl cme, fcme ? $fffa, $fffb cop failure reset none none cop rate selected ? $fff8, $fff9 unimplemented in struction trap none none none ? $fff6, $fff7 swi none none none ? $fff4, $fff5 xirq x bit none none ? $fff2, $fff3 irq i bit intcr irqen $f2 $fff0, $fff1 real-time inte rrupt i bit rtictl rtie $f0 $ffee, $ffef timer channel 0 i bit tmsk1 c0i $ee $ffec, $ffed timer channel 1 i bit tmsk1 c1i $ec $ffea, $ffeb timer channel 2 i bit tmsk1 c2i $ea $ffe8, $ffe9 timer channel 3 i bit tmsk1 c3i $e8 $ffe6, $ffe7 timer channel 4 i bit tmsk1 c4i $e6 $ffe4, $ffe5 timer channel 5 i bit tmsk1 c5i $e4 $ffe2, $ffe3 timer channel 6 i bit tmsk1 c6i $e2 $ffe0, $ffe1 timer channel 7 i bit tmsk1 c7i $e0 $ffde, $ffdf timer overflow i bit tmsk2 toi $de $ffdc, $ffdd pulse accumulato r overflow i bit pactl paovi $dc $ffda, $ffdb pulse accumulator input edge i bit pactl pai $da $ffd8, $ffd9 spi serial transfer complete i bit sp0cr1 spie $d8 $ffd6, $ffd7 sci 0 i bit sc0 cr2 tie, tcie, rie, ilie $d6 $ffd4, $ffd5 reserved i bit ? ? $d4 $ffd2, $ffd3 atd i bit atdctl2 ascie $d2 $ffd0, $ffd1 bdlc i bit bcr1 ie $d0 $ff80?$ffc1 reserved (not implemented) i bit ? ? $80?$c0 $ffc2?$ffc9 reserved (implemented) i bit ? ? $c2?$c8 $ffca, $ffcb pulse accumulator b overflow i bit pbctl pbovi $ca $ffcc, $ffcd modulus down counter underflow i bit mcctl mczi $cc $ffce, $ffcf reserved (implemented) i bit ? ? $ce
maskable interrupts m68hc12b family data sheet, rev. 9.1 freescale semiconductor 69 table 4-2. mc68hc(9)12bc32 interrupt vector map vector address interrupt source ccr mask local enable hprio value to elevate to highest i bit register bit(s) $fffe, $ffff reset none none none ? $fffc, $fffd cop clock monitor fail reset none copctl cme, fcme ? $fffa, $fffb cop failure reset none none cop rate selected ? $fff8, $fff9 unimplemented in struction trap none none none ? $fff6, $fff7 swi none none none ? $fff4, $fff5 xirq x bit none none ? $fff2, $fff3 irq i bit intcr irqen $f2 $fff0, $fff1 real-time inte rrupt i bit rtictl rtie $f0 $ffee, $ffef timer channel 0 i bit tmsk1 c0i $ee $ffec, $ffed timer channel 1 i bit tmsk1 c1i $ec $ffea, $ffeb timer channel 2 i bit tmsk1 c2i $ea $ffe8, $ffe9 timer channel 3 i bit tmsk1 c3i $e8 $ffe6, $ffe7 timer channel 4 i bit tmsk1 c4i $e6 $ffe4, $ffe5 timer channel 5 i bit tmsk1 c5i $e4 $ffe2, $ffe3 timer channel 6 i bit tmsk1 c6i $e2 $ffe0, $ffe1 timer channel 7 i bit tmsk1 c7i $e0 $ffde, $ffdf timer overflow i bit tmsk2 toi $de $ffdc, $ffdd pulse accumulato r overflow i bit pactl paovi $dc $ffda, $ffdb pulse accumulator input edge i bit pactl pai $da $ffd8, $ffd9 spi serial transfer complete i bit sp0cr1 spie $d8 $ffd6, $ffd7 sci 0 i bit sc0 cr2 tie, tcie, rie, ilie $d6 $ffd4, $ffd5 reserved i bit ? ? $d4 $ffd2, $ffd3 atd i bit atdctl2 ascie $d2 $ffd0, $ffd1 mscan wa keup i bit crier wupie $d0 $ffca?$ffcf reserved (not implemented) i bit ? ? $ca?$cf $ffc8?$ffc9 mscan errors i bit crier rwrnie, twrnie, rerrie, terrie, boffie, ovrie $c8 $ffc6, $ffc7 mscan rece ive i bit crier rxfie $c6 $ffc4, $ffc5 mscan transmit i bit ctcr txeie[2:0] $c4 $ff80, $ffc3 reserved (implemented) i bit ? ? $80?$c3
resets and interrupts m68hc12b family data sheet, rev. 9.1 70 freescale semiconductor 4.4 latching of interrupts xirq is always level triggered and irq can be selected as a level-triggered interrupt. these level-triggered interrupt pins should be released only during the appropriate interrupt service routine. generally, the interrupt service routi ne will handshake with the interrupting logic to release the pin. in this way, the mcu will never start the interrupt service se quence only to determine that there is no longer an interrupt source. in the event that this does occur, the trap vector will be taken. if irq is selected as an edge-triggered interrupt, the hold time of the level after the active edge is independent of when the interrupt is serviced. as long as the minimum hold time is met, the interrupt will be latched inside the mcu. in this case, the irq edge interrupt latch is cleared automatically when the interrupt is serviced. all of the remaining interrupts are latched by the mcu with a flag bit. these interrupt flags should be cleared during an interrupt service routine or when th e interrupts are masked by the i bit. by doing this, the mcu will never get an unknown interrupt source and take the trap vector. 4.5 interrupt control and priority registers this section describes the interrupt control and priority registers. 4.5.1 interrupt control register read: anytime write: varies from bit to bit irqe ? irq edge-sensitive only bit irqe can be written once in normal modes. in spec ial modes, irqe can be written anytime, but the first write is ignored. 1 = irq pin responds only to falling edges. 0 = irq pin responds to low levels. irqen ? external irq enable bit irqen can be written anytime in all modes. the irq pin has an internal pullup. 1 = irq pin connected to interrupt logic 0 = irq pin disconnected from interrupt logic dly ? oscillator startup delay on exit from stop mode bit dly can be written once in normal modes. in special modes, dly can be written anytime. the delay time of about 4096 cycles is based on the e-clock rate. 1 = stabilization delay on exit from stop mode 0 = no stabilization delay on exit from stop mode address: $001e bit 7654321bit 0 read: irqeirqendly00000 write: reset:01100000 figure 4-1. interrupt control register (intcr)
resets m68hc12b family data sheet, rev. 9.1 freescale semiconductor 71 4.5.2 highest priority i interrupt register read: anytime write: only if i bit in ccr = 1 (interrupts inhibited) to give a maskable interrupt source highest priority, wr ite the low byte of the vector address to the hprio register. for example, writing $f0 to hprio assigns highest maskable interrupt priority to the real-time interrupt timer ($fff0). if an unimplemented vector address or a non-i-masked vector address (a value higher than $f2) is written, then irq is the default highest priority interrupt. 4.6 resets there are four possible sources of rese t. por and external reset on the reset pin share the normal reset vector. cop reset and the clock monitor reset eac h has a vector. entry into reset is asynchronous and does not require a clock, but the mcu cannot sequence out of reset without a system clock. 4.6.1 power-on reset (por) a positive transition on v dd causes a por. an external voltage level detector or other external reset circuits are the usual source of reset in a system. th e por circuit only initializes internal circuitry during cold starts and cannot be used to force a reset as system voltage drops. 4.6.2 external reset the cpu distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than eight e-clock cycles after an internal device releases reset. when a reset condition is sensed, the reset pin is driven low by an internal device for about 16 e-clock cycles, then released. eight e-clock cycles later it is sampled. if the pin is still held low, the cpu assumes that an external reset has occurred. if the pin is high, it indica tes that the reset was initiated internally by either the cop system or the clock monitor. to prevent a cop or clock monitor reset from being detected during an external reset, hold the reset pin low for at least 32 cycles. an exter nal resistor-capacitor (rc) power-up delay circuit on the reset pin is not recommended because circuit charge time can cause t he mcu to misinterpret the type of reset that has occurred. 4.6.3 computer operat ing properly (cop) reset the mcu includes a cop system to help prot ect against software fail ures. when cop is enabled, software must write $55 and $aa (in this order) to the coprst register to keep a watchdog timer from timing out. other instructions may be executed between these writes. a write of any value other than $55 or $aa or software failing to execute the sequence properly causes a cop reset to occur. address: $001f bit 7654321bit 0 read: 1 1 psel5 psel4 psel3 psel2 psel1 0 write: reset:11110010 figure 4-2. highest priority i interrupt register (hprio)
resets and interrupts m68hc12b family data sheet, rev. 9.1 72 freescale semiconductor 4.6.4 clock monitor reset if clock frequency falls below a predetermined limit wh en the clock monitor is enabled, a reset occurs. 4.7 effects of reset when a reset occurs, mcu registers and control bits are changed to known startup states, as described here. 4.7.1 operating mode and memory map the states of the bkgd, moda, and modb pins dur ing reset determine the operating mode and default memory mapping. the smodn, moda, and modb bits in the mode register reflect the status of the mode-select inputs at the rising edge of reset. oper ating mode and default maps can subsequently be changed according to strictly defined rules. 4.7.2 clock and wa tchdog control logic reset enables the cop watchdog with the cr2?cr0 bits set for the shortest timeout period. the clock monitor is disabled. the rtif flag is cleared and automatic hardware interrupts are masked. the rate control bits are cleared and must be initialized before t he return-from-interrupt (rti) system is used. the dly control bit is set to specify an oscillator startup delay upon recovery from stop mode. 4.7.3 interrupts reset initializes the hprio register with the value $f2, causing the irq pin to have the highest i-bit interrupt priority. the irq pin is configured for level-sensitive operation (for wired-or systems). however, the i and x bits in th e ccr are set, masking irq and xirq interrupt requests. 4.7.4 parallel input/output (i/o) if the mcu comes out of reset in an expanded mode, port a and port b are the multiplexed address/data bus. port e pins are normally used to control the external bus. the port e as signment register (pear) affects port e pin operation. if the mcu comes out of reset in a single-chip mode, all ports are configured as general-purpose high-impedance inputs. 4.7.5 central pr ocessing unit (cpu) after reset, the cpu fetches a vector from the appropriate address and begins executing instructions. the stack pointer and other cpu registers are indetermi nate immediately after reset. the condition code register (ccr) x and i interrupt mask bits are set to mask any interrupt requests. the s bit is also set to inhibit the stop instruction. 4.7.6 memory after reset, the internal register block is locate d at $0000?$01ff, the regist er-following space is at $0200?$03ff, and ram is at $0800?$0bff. eeprom is loca ted at $0d00?$0fff. flash eeprom/rom is located at $8000?$ffff in single-ch ip modes and at $0000?$7fff (but disabled) in expanded modes.
interrupt recognition m68hc12b family data sheet, rev. 9.1 freescale semiconductor 73 4.7.7 other resources the timer, serial communications interface (sci), serial peripheral interface (spi), byte data link controller (bdlc), pulse-width modulator (pwm), analog-to-digit al converter (atd), and mscan are off after reset. 4.8 interrupt recognition once enabled, an interrupt request can be recognized at any time afte r the i bit in the ccr is cleared. when an interrupt request is recognized, the cpu re sponds at the completion of the instruction being executed. interrupt latency varies according to the num ber of cycles required to complete the instruction. some of the longer instructions can be interrupted and resume normally after servicing the interrupt. when the cpu begins to service an interrupt request, it: clears the instruction queue calculates the return address stacks the return address and the contents of the cpu registers as shown in table 4-3 after stacking the ccr, the cpu: sets the i bit to prevent other interrupts from disrupting the interrupt service routine sets the x bit if an xirq interrupt request is pending fetches the interrupt vector for the highest-prio rity request that was pending at the beginning of the interrupt sequence begins execution of the interrupt service routine at the location pointed to by the vector if no other interrupt request is pending at the end of the interrupt service routine, a return-from-interrupt (rti) instruction recovers the stacked values. progra m execution resumes program at the return address. if another interrupt request is pending at the end of an interrupt service routine, the rti instruction recovers the stacked values. however, the cpu then: adjusts the stack pointer to point aga in at the stacked ccr location, sp ? 9 fetches the vector of the pending interrupt begins execution of the interrupt service routine at the location pointed to by the vector table 4-3. stacking order on entry to interrupts memory location stacked values sp ? 2 rtn h : rtn l sp ? 4 y h : y l sp ? 6 x h : x l sp ? 8 b : a sp ? 9 ccr
resets and interrupts m68hc12b family data sheet, rev. 9.1 74 freescale semiconductor
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 75 chapter 5 operating modes and resource mapping 5.1 introduction the mcu can operate in eight different modes. ea ch mode has a different default memory map and external bus configuration. after reset, most system resources can be mapped to other addresses by writing to the appropriate control registers. 5.2 operating modes the states of the bkgd, modb, and moda pins during reset determine the operating mode after reset. the smodn, modb, and moda bits in the mode r egister show current o perating mode and provide limited mode switching during operation. the states of the bkgd, modb, and moda pins are latched into these bits on the rising edge of the reset signal. during reset an active pullup is connected to the bkgd pin (as input) and active pulldowns are connected to the modb and moda pins. if an open occurs on any of these pins, the device will operate in normal single-chip mode. the two basic types of operating modes are: 1. normal modes ? some registers and bits are protected against accidental changes. 2. special modes ? protected control registers and bits are allowed greater access for special purposes such as testing and emulation. a system development and debug feature, background debug mode (bdm) is available in all modes. in special single-chip mode, bdm is active immediately after reset. table 5-1. mode selection bkgd modb moda mode port a port b 0 0 0 special single chip general-purpose i/o general-purpose i/o 0 0 1 special expanded narrow addr[15:8] data[7:0] addr[7:0] 0 1 0 special peripheral addr data addr data 0 1 1 special expanded wide addr data addr data 1 0 0 normal single chip general-purpose i/o general-purpose i/o 1 0 1 normal expanded narrow addr[15:8] data[7:0] addr[7:0] 110 reserved (forced to peripheral) ?? 1 1 1 normal expanded wide addr data addr data
operating modes and resource mapping m68hc12b family data sheet, rev. 9.1 76 freescale semiconductor 5.2.1 normal operating modes these modes provide three operat ing configurations. background debugging is available in all three modes, but must first be enabled for some operati ons by means of a bdm command. bdm can then be made active by another bdm command. 5.2.1.1 normal expanded wide mode the 16-bit external address and data buses us e ports a and b. addr15?addr8 and data15?data8 are multiplexed on port a. addr7?addr0 and data7?data0 are multiplexed on port b. 5.2.1.2 normal expanded narrow mode the 16-bit external address bus uses port a for the high byte and port b for the low byte. the 8-bit external data bus uses port a. addr15?addr8 and data7?data0 are multiplexed on port a. 5.2.1.3 normal single-chip mode normal single-chip mode has no external buses. po rts a, b, and e are configured for general-purpose input/output (i/o). port e bits 1 and 0 are input onl y with internal pullups and the other 22 pins are bidirectional i/o pins that are in itially configured as high-impedance i nputs. port e pullups are enabled on reset. port a and b pullups are disabled on reset. 5.2.2 special operating modes special operating modes are commonly used in factory testing and system development. 5.2.2.1 special expanded wide mode this mode is for emulation of normal expanded wide mode and emulation of normal single-chip mode with a 16-bit bus. the bus-control pins of port e are all configured for their bus-control output functions rather than general-purpose i/o. 5.2.2.2 special expanded narrow mode this mode is for emulation of normal expanded narro w mode. external 16-bit data is handled as two back-to-back bus cycles, one for the high byte followed by one for the low byte. internal operations continue to use full 16-bit data paths. 5.2.2.3 special single-chip mode this mode can be used to force the mcu to active bdm mode to allow system debug through the bkgd pin. the mcu does not fetch the reset vector and exec ute application code as it would in other modes. instead, the active background mode is in control of cpu execution and bdm firmware waits for additional serial commands through the bkgd pin. there are no external address and data buses in this mode. the mcu operates as a stand-alone device and all program and data space are on-chip. external port pins can be used for general-purpose i/o.
internal resource mapping m68hc12b family data sheet, rev. 9.1 freescale semiconductor 77 5.2.2.4 special peripheral mode the cpu is not active in this mode. an external master can control on-chip peripherals for testing purposes. it is not possible to change to or from this mode without going through reset. background debugging should not be used while the mcu is in s pecial peripheral mode as internal bus conflicts between bdm and the external master can cause improper operation of both modes. 5.2.3 background debug mode background debug mode (bdm) is an auxiliary operat ing mode that is used for system development. bdm is implemented in on-chip hardware and provides a full set of debug operations. some bdm commands can be executed while the cpu is operatin g normally. other bdm commands are firmware based and require the bdm firmware to be enabled and active for execution. in special single-chip mode, bdm is enabled and active immediately out of reset. bdm is available in all other operating modes, but must be enabled before it can be activated. bdm should not be used in special peripheral mode because of potential bus conflicts. once enabled, background mode can be made active by a serial command sent via the bkgd pin or execution of a cpu12 bgnd instruction. while backg round mode is active, the cpu can interpret special debugging commands, read and write cpu registers, peripheral registers, and locations in memory. while bdm is active, the cpu executes code loca ted in a small on-chip rom mapped to addresses $ff00 to $ffff; bdm control registers are accessible at addresses $ff00 to $ff06. the bdm rom replaces the regular system vectors while bdm is ac tive. while bdm is active, the user memory from $ff00 to $ffff is not in the map except through serial bdm commands. bdm allows read and write access to internal memo ry-mapped registers and ram and read access to eeprom, flash eeprom, or rom without interrupting the application code executing in the cpu. this non-intrusive mode uses dead bus cycl es to access the memory and in most cases will remain cycle deterministic. refer to 18.3 background debug mode (bdm) for more details. 5.3 internal resource mapping the internal register block, ram, flash eeprom /rom, and eeprom have default locations within the 64-kbyte standard address space but may be reassigned to other locations during program execution by setting bits in mapping registers initrg, init rm, and initee. during normal operating modes, these registers can be written once. it is advisable to exp licitly establish these resource locations during the initialization phase of program execution, even if def ault values are chosen, to protect the registers from inadvertent modification later. writes to the mapping registers go into effect between the cycle that follows the write and the cycle after that. to assure that there are no unintended operat ions, a write to one of these registers should be followed with a no operation (nop) instruction. if conflicts occur when mapping resources, the regi ster block will take precedence over the other resources; ram, flash eeprom/rom, or eeprom addres ses occupied by the register block will not be available for storage. when active, bdm rom takes precedence over other resources, although a conflict between bdm rom and register space is not possible. table 5-2 shows resource mapping precedence. in expanded modes, all address space no t utilized by internal resources is by default external memory.
operating modes and resource mapping m68hc12b family data sheet, rev. 9.1 78 freescale semiconductor 5.4 mode and resour ce mapping registers this section describes the mode and resource mapping registers. 5.4.1 mode register the mode register (mode) controls the mcu opera ting mode and various conf iguration options. this register is not in the map in peripheral mode. read: anytime write: varies from bit to bit smodn, modb, moda ? mode select special, b, and a bits these bits show the current operating mode and reflect the status of the bkgd, modb, and moda input pins at the rising edge of reset. smodn can be written only if smodn = 0 (in special modes) but the first write is ignored; modb, moda may be written once if smodn = 1; anytime if smodn = 0, except that special peripheral and reserved modes cannot be selected. table 5-2. mapping precedence precedence resource 1 bdm rom (if active) 2 register space 3ram 4 eeprom 5 flash eeprom/rom 6external memory address: $000b bit 7654321bit 0 read: smodn modb moda estr ivis ebswai 0 eme write: reset states: normal expanded narrow: 1 0 110000 normal expanded wide:11110000 special expanded narrow: 0 0 111001 special expanded wide:01111001 peripheral:01011001 normal single-chip:10010000 special single-chip:00011001 figure 5-1. mode register (mode)
mode and resource mapping registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 79 estr ? e clock stretch enable bit estr determines if the e clock behaves as a simple free-running clock or as a bus control signal that is active only for external bus cycles. estr is al ways 1 in expanded modes since it is required for address demultiplexing and must follow stretched cycles. 1 = e stretches high during external access cy cles and low during non-visible internal accesses 0 = e never stretches (always free running) normal modes: write once special modes: write anytime ivis ? internal visibility bit ivis determines whether internal addr/data, r/w , and lstrb signals can be seen on the bus during accesses to internal locations. in special expanded narrow mode, it is possible to configure the mcu to show internal accesses on an external 16-bit bus. the ivis control bit must be set to 1. when the system is configured this way, visible internal accesses are shown as if the mcu was configured for expanded wide mode, but normal external accesses operate as if the bus in narrow mode. in normal expanded narrow mode, internal visibility is not allowed and ivis is ignored. 1 = internal bus operations visible on external bus 0 = no visibility of internal bus operations on external bus normal modes: write once special modes: write anytime except the first time ebswai ? external bus module stop in wait bit this bit controls access to the external bus in terface when in wait mode. the module delays before shutting down in wait mode to allow for final bus activity to complete. 1 = external bus shut down during wait mode 0 = external bus and registers continue functioning in wait mode. normal modes: write anytime special modes: write never eme ? emulate port e bit removing the registers from the map allows the us er to emulate the function of these registers externally. in single-chi p mode, port e data register (porte) and port e data direction register (ddre) are always in the map regardless of the state of this bit. 1 = porte and ddre removed from the memory map (expanded mode) 0 = porte and ddre in the memory map normal modes: write once special modes: write anytime except the first time
operating modes and resource mapping m68hc12b family data sheet, rev. 9.1 80 freescale semiconductor 5.4.2 register initialization register after reset, the 512-byte register block resides at location $0000 but can be reassigned to any 2-kbyte boundary within the standard 64-kbyte address space. mapping of internal registers is controlled by five bits in the register initialization register (initrg). the register block occupies the first 512 bytes of the 2-kbyte block. read: anytime write: once in normal modes; anytime in special modes reg15?reg11 ? register position bits these bits specify the upper five bi ts of the 16-bit register address. mmswai ? memory mapping interface stop in wait control bit this bit controls access to the memory mapping interface when in wait mode. 0 = memory mapping interface continues to function in wait mode. 1 = memory mapping interface access shuts down in wait mode. normal modes: write anytime special modes: write never 5.4.3 ram initialization register after reset, addresses of the 1-kbyte ram array begin at location $0800 but can be assigned to any 2-kbyte boundary within the standard 64-kbyte address sp ace. mapping of internal ram is controlled by five bits in the ram initialization register (initrm). the ram array occupies the first 1 kbyte of the 2-kbyte block. read: anytime write: once in normal modes; anytime in special modes ram15?ram11 ? ram position bits these bits specify the upper five bits of the 16-bit ram address. address: $0011 bit 7654321bit 0 read: reg15reg14reg13reg12reg11 0 0 mmswai write: reset:00000000 figure 5-2. register initialization register (initrg) address: $0010 bit 7654321bit 0 read: ram15 ram14 ram13 ram12 ram11 0 0 0 write: reset:00001000 figure 5-3. ram initialization register (initrm)
mode and resource mapping registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 81 5.4.4 eeprom initia lization register the mcu has 768 bytes of eeprom which are activate d by the eeon bit in the eeprom initialization register (initee). mapping of internal eeprom is cont rolled by four bits in the init ee register. after reset, eeprom address space begins at location $0d00 but can be mapped to any 4-kbyte boundary within the standard 64-kbyte address space. read: anytime write: varies from bit to bit ee15?ee12 ? internal eeprom position bits these bits specify the upper four bits of the 16-b it eeprom address. write once in normal modes or anytime in special modes. eeon ? eeprom on bit eeon allows read access to the eeprom array. eeprom control register s can be accessed and eeprom locations can be pr ogrammed or erased regardless of the state of eeon. eeon is forced to 1 in single-chip modes. write only in expanded and peripheral modes. 1 = eeprom in memory map 0 = eeprom removed from memory map 5.4.5 miscellaneous mapp ing control register additional mapping controls are available that can be used in co njunction with flash eeprom/rom and memory expansion. the 32-kbyte flash eeprom/rom can be mapped to either the upper or lower half of the 64-kbyte address space. when mapping conflicts occur, registers, ram, and eeprom have priority over flash eeprom. note only the mc68hc912b32 contains flash eeprom. the mc68hc12be32 contains rom. to use memory expansion, the part must be operated in one of the expanded modes. address: $0012 bit 7654321bit 0 read: ee15 ee14 ee13 ee12 0 0 0 eeon write: reset:00000001 figure 5-4. eeprom initiali zation register (initee)
operating modes and resource mapping m68hc12b family data sheet, rev. 9.1 82 freescale semiconductor read: anytime write: once in normal modes; anytime in special modes ndrf ? narrow data bus for register-following map bit this bit enables a narrow bus feature for the 512-byte register-following map. in expanded narrow (8-bit) modes, single-chip modes, and peripheral mode, ndrf has no e ffect. the register-following map always begins at the byte foll owing the 512-byte register map. if the registers are moved, this space moves also. 1 = register-following map space acts the same as an 8-bit external data bus. 0 = register-following map space acts as a full 16-bit external data bus. rfstr1 and rfstr0 ? register-following stretch bits these bits determine the amount of clock stretch on accesses to the 512-byte register-following map. it is valid regardless of the state of the ndrf bit. in single-chip and peripheral modes, these bits have no meaning or effect. see table 5-3 . exstr1 and exstr0 ? external access stretch bit 1 and bit 0 these bits determine the amount of clock stretch on accesses to the external address space. in single-chip and peripheral modes, these bits have no meaning or effect. address: $0013 bit 7654321bit 0 read: 0 ndrf rfstr1 rfstr0 exstr1 exstr0 maprom romon write: reset states: expanded modes: 00001100 single-chip modes: 00001111 figure 5-5. miscellaneous mapping control register (misc) table 5-3. register-following stretch bit function rfstr1 and rfstr0 e clocks stretched 00 0 01 1 10 2 11 3 table 5-4. expanded stretch bit function exstr1 and exstr0 e clocks stretched 00 0 01 1 10 2 11 3
memory map m68hc12b family data sheet, rev. 9.1 freescale semiconductor 83 maprom ? flash eeprom/rom map bit this bit determines the location of the on-chip flash eeprom/rom. in expanded modes, it is reset to 0. in single-chip modes, it is reset to 1. if romon is 0, this bit has no meaning or effect. 1 = flash eeprom/rom is located from $8000 to $ffff. 0 = flash eeprom/rom is located from $0000 to $7fff. romon ? flash eeprom/rom enable bit in expanded modes, romon is reset to 0. in single-chi p modes, it is reset to 1. if the internal ram, registers, eeprom, or bdm rom (if active) ar e mapped to the same space as the flash eeprom/rom, they will have priori ty over the flash eeprom/rom. 1 = enables the flash eeprom/rom in the memory map 0 = disables the flash eeprom/rom in the memory map 5.5 memory map figure 5-6 illustrates the memory map for each m ode of operation immediately after reset. figure 5-6. memory map bdm if active $8000 $ffff $ffff flash eeprom/rom $0000 $0800 $0d00 $0fff $ff00 $0000 $01ff $0800 single-chip special single-chip normal expanded $8000 vectors vectors vectors $ff00 $f000 768 bytes eeprom map to any 4-k space 1-kbyte ram map to any 2-k space registers map to any 2-k space $ffff $ffc0 $0bff map with maprom bit $0d00 512 bytes $0000 $7fff in misc register to $0000?$7fff or $8000?$ffff $0200 $03ff register following space 512 bytes
operating modes and resource mapping m68hc12b family data sheet, rev. 9.1 84 freescale semiconductor
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 85 chapter 6 bus control and input/output (i/o) 6.1 introduction internally, the mcu has full 16-bit data paths, but depending upon the operating mode and control registers, the external bus may be eight or 16 bits. there are cases where 8-bit and 16-bit accesses can appear on adjacent cycles using the lstrb signal to indicate 8-bit or 16-bit data. 6.2 detecting access type from external signals the external signals lstrb , r/w , and a0 can be used to determine the type of bus access that is taking place. accesses to the internal ram modul e are the only accesses that produce lstrb =a0=1, because the internal ram is specif ically designed to allow misaligned 16- bit accesses in a single cycle. in these cases, the data for the address that was accessed is on the low half of the data bus and the data for address +1 is on the high half of the data bus (data order is swapped). 6.3 registers under certain conditions, not all registers are visible in the memory map. in special peripheral mode, the first 16 registers associated with bus expansion are removed from the memory map. in expanded modes, some or all of port a, port b, and port e are used for expansion buses and control signals. to allow emulation of the single-chip functions of these ports, some of these registers must be rebuilt in an external port replacement unit. in any expanded mode, port a and port b are used for address and data lines so registers for these ports, as well as the data direction registers for these ports, are removed fr om the on-chip memory map and become external accesses. in any expanded mode, port e pins may be needed for bus control (for example, eclk and r/w ). to regain the single-chip functions of port e, the emulat e port e (eme) control bit in the mode register may table 6-1. detecting access type lstrb a0 r/w type of access 1 0 1 8-bit read of an even address 0 1 1 8-bit read of an odd address 1 0 0 8-bit write to an even address 0 1 0 8-bit write to an odd address 0 0 1 16-bit read of an even address 1 1 1 16-bit read of an odd address (low/high data swapped) 0 0 0 16-bit write to an even address 1 1 0 16-bit write to an odd address (low/high data swapped)
bus control and input/output (i/o) m68hc12b family data sheet, rev. 9.1 86 freescale semiconductor be set. in this special case of expanded mode and eme set, the port e data register (porte) and port e data direction register (ddre) are removed from the on-chip memory map and become external accesses so port e may be rebuilt externally. 6.3.1 port a data register read: anytime, if register is in the map write: anytime, if register is in the map bits pa7?pa0 are associated with addresses addr 15?addr8 and data15?data8. when this port is not used for external addresses and data, such as in single-chip mode, these pins can be used as general-purpose input/output (i/o). ddra determines the primary direction of each pin. this register is not in the on-chip map in expanded and peripheral modes. 6.3.2 port a data direction register read: anytime, if register is in the map write: anytime, if register is in the map this register determines the primary direction for each port a pin when functioni ng as a general-purpose i/o port. ddra is not in the on-chip map in expanded and peripheral modes. 1 = associated pin is an output. 0 = associated pin is a high-impedance input. address: $0000 bit 7654321bit 0 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset expanded wide and peripheral: addr15 data15 addr14 data14 addr13 data13 addr12 data12 addr11 data11 addr10 data10 addr9 data9 addr8 data8 expanded narrow: addr15 data15/7 addr14 data14/6 addr13 data13/5 addr12 data12/4 addr11 data11/3 addr10 data10/2 addr9 data9/1 addr8 data8/0 figure 6-1. port a data register (porta) address: $0002 bit 7654321bit 0 read: dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 write: reset:00000000 figure 6-2. port a data direction register (ddra)
registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 87 6.3.3 port b data register read: anytime, if register is in the map write: anytime, if register is in the map bits pb7?pb0 are associated with addresses ad dr7?addr0 and data7?data 0. when port b is not used for external addresses and data such as in single-chip mode, these pins can be used as general-purpose i/o. ddrb determines the primary direction of each pin. this register is not in the on-chip map in expanded and peripheral modes. 6.3.4 port b data direction register read: anytime, if register is in the map write: anytime, if register is in the map this register determines the primary direction for each port b pin when functioni ng as a general-purpose i/o port. ddrb is not in the on-chip map in expanded and peripheral modes. 1 = associated pin is an output. 0 = associated pin is a high-impedance input. address: $0001 bit 7654321bit 0 read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset alternate functions: expanded wide and peripheral: addr7 data7 addr6 data6 addr5 data5 addr4 data4 addr3 data3 addr2 data2 addr1 data1 addr0 data0 expanded narrow: addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 figure 6-3. port b data register (portb) address: $0003 bit 7654321bit 0 read: ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 write: reset:00000000 figure 6-4. port b data direction register (ddrb)
bus control and input/output (i/o) m68hc12b family data sheet, rev. 9.1 88 freescale semiconductor 6.3.5 port e data register read: anytime, if register is in the map write: anytime, if register is in the map this register is associated with external bus control signals and interrupt inputs including: data bus enable (dbe ) mode select (modb/ipipe1 and moda/ipipe0) e clock data size (lstrb /taglo ) read/write (r/w ) irq xirq when the associated pin is not used for one of th ese specific functions, the pin can be used as general-purpose i/o. the port e assi gnment register (pear) selects th e function of each pin. ddre determines the primary direction of each port e pin when configured to be general-purpose i/o. some of these pins have software selectable pullups (dbe , lstrb , r/w , and xirq ). a single control bit enables the pullups for all these pins which are configured as inputs. irq always has a pullup. this register is not in the map in peripheral mode or expanded modes when the eme bit is set. 6.3.6 port e data direction register read: anytime, if register is in the map write: anytime, if register is in the map this register determines the primary direction for each port e pin configured as general-purpose i/o. 1 = associated pin is an output. 0 = associated pin is a high-impedance input. address: $0008 bit 7654321bit 0 read: pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 write: reset:00000000 alternate function: dbe modb or ipipe1 moda or ipipe0 eclk lstrb or taglo r/w irq xirq figure 6-5. port e data register (porte) address: $0009 bit 7654321bit 0 read: dde7 dde6 dde5 dde4 dde3 dde2 00 write: reset:00000000 = unimplemented figure 6-6. port e data direction register (ddre)
registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 89 pe1 and pe0 are associated with xirq and irq and cannot be configured as outputs. these pins can be read regardless of whether the alternate interrupt functions are enabled. this register is not in the map in peripheral mode and expanded modes while the eme control bit is set. 6.3.7 port e assignment register read: anytime, if register is in the map write: varies from bit to bit, if register is in the map the pear register is used to choose between the g eneral-purpose i/o functions and the alternate bus control functions of port e. when an alternate control function is selected, the associated ddre bits are overridden. the reset condition of this register depends on the mode of operation because bus-control signals are needed immediately after reset in some modes. in normal single-chip mode , no external bus control signals are needed, so all of port e is configured for general-purpose i/o. in special single-chip mode , the e clock is enabled as a timing reference, and the other bits of port e are configured for general-purpose i/o. in normal expanded modes , the reset vector is located in external memory. the e clock may be required for this access but r/w is only needed by the system when there are external writable resources. therefore, in normal expanded modes, only the e clock is configured for its alternate bus control function and the other bits of port e are configured for gen eral-purpose i/o. if the norm al expanded system needs any other bus-control signals, pear would need to be written before any access that needed the additional signals. in special expanded modes , ipipe1, ipipe0, e, r/w , and lstrb are configured as bus-control signals. in peripheral mode , the pear register is not accessible for reads or writes. ndbe ? no data bus enable bit normal: write once special: write anytime except the first time 1 = pe7 used for general-purpose i/o 0 = pe7 used for external cont rol of data enables on memories address: $000a bit 7654321bit 0 read: ndbe cgmte pipoe neclk lstre rdwe 00 write: reset states: normal single-chip:10010000 special single-chip:00101100 normal expanded: 00000000 special expanded: 00101100 peripheral:11010000 = unimplemented figure 6-7. port e assignment register (pear)
bus control and input/output (i/o) m68hc12b family data sheet, rev. 9.1 90 freescale semiconductor cgmte ? cgm test output enable normal: write once special: write anytime except the first time. this bit is read at anytime. 1 = pe6 is a test signal output from the cgm m odule (no effect in single chip or normal expanded modes). pipoe = 1 overrides this function and fo rces pe6 to be a pipe status output signal. 0 = pe6 is a general-purpose i/o or pipe output. pipoe ? pipe signal output enable bit normal: write once special: write anytime except the first time. this bit has no effect in single chip modes. 1 = pe6?pe5 are outputs and indicate state of instruction queue. 0 = pe6?pe5 are general-purpose i/o. neclk ? no external e clock bit in expanded modes, writes to this bit have no effect . e clock is required for demultiplexing the external address; neclk remains 0 in expanded modes. neclk can be written once in normal single-chip mode and can be written anytime in special single-chip mode. 1 = pe4 is a general-purpose i/o pin. 0 = pe4 is the external e clock pin subject to this limitation: in si ngle-chip modes, pe4 is general-purpose i/o unless neclk = 0 and either ivis = 1 or estr = 0. a 16-bit write to pear:mode can configure all three bits in one operation. lstre ? low strobe (lstrb ) enable bit normal: write once special: write anytime except the first time this bit has no effect in single-chip modes or normal expanded narrow mode. 1 = pe3 is configured as the lstrb bus-control output. 0 = pe3 is a general-purpose i/o pin. lstrb is used during external writes. after reset in normal expanded mode, lstrb is disabled. if needed, it should be enabled before external writes. external reads do not normally need lstrb because all 16 data bits can be driven even if the mcu only needs eight bits of data. tag l o is a shared function of the pe3/lstrb pin. in special expanded modes with lstre set and the bdm instruction tagging on, a 0 at the falling edge of e tags the instruction word low byte being read into the instruction queue. rdwe ? read/write enable bit normal: write once special: write anytime except the first time this bit has no effect in single-chip modes. 1 = pe2 configured as r/w pin 0 = pe2 configured as general-purpose i/o pin r/w is used for external writes. after reset in norm al expanded mode, it is di sabled. if needed, it should be enabled before any external writes.
registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 91 6.3.8 pullup control register read: anytime, if register is in the map write: anytime, if register is in the map these bits select pullup resistors for any pin in the corresponding port that is currently configured as an input. this register is not in the map in peripheral mode. pupe ? pullup port e enable bit pin pe1 always has a pullup. pins pe6, pe5, and pe4 never have pullups. 1 = enable port e pullups on pe7, pe3, pe2, pe1, and pe0 0 = disable port e pullups on pe7, pe3, pe2, pe1, and pe0 pupb ? pullup port b enable bit 1 = enable pullups for all port b input pins 0 = disable port b pullups this bit has no effect if port b is used as par t of the address/data bus (pullups are inactive). pupa ? pullup port a enable bit 0 = disable port a pullups 1 = enable pullups for all port a input pins this bit has no effect, if port a is used as par t of the address/data bus (pullups are inactive). address: $000c bit 7654321bit 0 read: 0 0 0 pupe 00 pupb pupa write: reset:00010000 = unimplemented figure 6-8. pullup control register (pucr)
bus control and input/output (i/o) m68hc12b family data sheet, rev. 9.1 92 freescale semiconductor 6.3.9 reduced dr ive of i/o lines read: anytime, if register is in the map write: once in normal modes; anytime, except the first time, in special modes these bits select reduced drive for the associated port pins. this gives reduced power consumption and reduced radio frequency interference (rfi) with a slight increase in transition ti me (depending on loading). the reduced drive function is independent of which f unction is being used on a particular port. this register is not in the map in peripheral mode. rdpe ? reduced drive of port e bit 1 = reduced drive for all port e output pins 0 = full drive for all port e output pins rdpb ? reduced drive of port b bit 1 = reduced drive for all port b output pins 0 = full drive for all port b output pins rdpa ? reduced drive of port a bit 1 = reduced drive for all port a output pins 0 = full drive for all port a output pins address: $000d bit 7654321bit 0 read:0000 rdpe 0 rdpb rdpa write: reset:00000000 = unimplemented figure 6-9. reduced drive of i/o lines (rdriv)
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 93 chapter 7 eeprom 7.1 introduction the mcu is electrically erasable, programmable r ead-only memory (eeprom) serves as a 768-byte non-volatile memory which can be used for frequently accessed static data or as fast access program code. the mcu?s eeprom is arranged in a 16-bit configur ation. the eeprom array may be read as either bytes, aligned words, or misaligned words. access time is one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations. programming is by byte or aligned word. attempts to program or erase misaligned words will fail. only the lower byte will be latched and programmed or erased. programmin g and erasing of the user eeprom can be done in all operating modes. each eeprom byte or aligned word must be er ased before programming. the eeprom module supports byte, aligned word, row (32 bytes), or bulk erase, all using the internal charge pump. bulk erasure of odd and even rows is also possible in test modes; the erased state is $ff. the eeprom module has hardware interlocks which protect stored data from corruption by accidentally enabling the program/erase voltage. programming voltage is derived from the internal v dd supply with an internal charge pump. the eeprom has a minimum program/erase life of 10,000 cycles over the complete operating temperature range. 7.2 eeprom programmer?s model the eeprom module consists of tw o separately addressable sections. the first is a 4-byte memory mapped control register block used for control, testing, and configuration of the eeprom array. the second section is the eeprom array itself. at reset, the 4-byte register section starts at address $00f0 and the eeprom array is located from addresses $0d00 to $0fff (see figure 7-1 ). for information on remapping the register block and eeprom address space, refer to chapter 5 operating modes and resource mapping . read access to the memory array section can be ena bled or disabled by the eeon control bit in the eeprom initialization register (initee). this feat ure allows the access of memory mapped resources that have lower priority than the eeprom memory array. eeprom control registers can be accessed and eeprom locations may be programmed or erased regardless of the state of eeon. using the normal eeprog control, it is possible to continue program/e rase operations during wait. for lowest power consumption during wait, stop program/erase by turning off eepgm. if the stop mode is entered during programming or erasing, program/erase voltage will be turned off automatically and t he resistor-capacitor (rc) clock (if enabled) is stopped. however, the eepgm control bit will remain set. when stop mode is terminated, the program/erase voltage will be turned back on automatically if eepgm is set.
eeprom m68hc12b family data sheet, rev. 9.1 94 freescale semiconductor at bus frequencies below 1 mhz, the rc clock must be turned on for program/erase. figure 7-1. eeprom block protect mapping 7.3 eeprom control registers this section describes the eeprom control registers. 7.3.1 eeprom module c onfiguration register eeswai ? eeprom stops in wait mode bit 0 = module is not affected during wait mode. 1 = module ceases to be clocked during wait mode. this bit should be cleared if the wait mode vectors are mapped in the eeprom array. protlck ? block protect write lock bit 0 = block protect bits and bulk erase protection bit can be written. 1 = block protect bits are locked. read anytime. write once in normal modes (smodn = 1); set and clear anytime in special modes (smodn = 0). eerc ? eeprom charge pump clock bit 0 = system clock is used as clock source for the internal charge pump. internal rc oscillator is stopped. 1 = internal rc oscillator drives the charge pump. the rc oscillator is required when the system bus clock is lower than f prog . read and write anytime. address: $00f0 bit 7654321bit 0 read: 11111 eeswai protlck eerc write: reset:11111100 figure 7-2. eeprom module configuration register (eemcr) bprot0 bprot1 bprot2 bprot3 bprot4 $_f00 $_e00 $_d00 $_f80 $_fc0 256 bytes 256 bytes 128 bytes
eeprom control registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 95 7.3.2 eeprom bloc k protect register the eeprom block protect register (eeprot ) prevents accidental writes to eeprom. read anytime. write anytime if eepgm = 0 and protlck = 0. bprot4?bprot0 ? eeprom block protection bit 0 = associated eeprom block c an be programmed and erased. 1 = associated eeprom block is protec ted from being pr ogrammed and erased. cannot be modified while programmi ng is taking place (eepgm = 1). 7.3.3 eeprom test register read anytime. write in special modes only (smodn = 0). these bits are used for test purposes only. in normal modes, the bits are forced to 0. eeodd ? odd row programming bit 0 = odd row bulk programming/erasing is disabled. 1 = bulk program/erase all odd rows. refers to a physical location in the array rather than an odd byte address eeven ? even row programming bit 0 = even row bulk programming/erasing is disabled. 1 = bulk program/erase all even rows. refers to a physical location in the array rather than an even byte address. address: $00f1 bit 7654321bit 0 read: 1 1 1 brprot4 brprot3 brprot2 brprot1 brprot0 write: reset:11111111 figure 7-3. eeprom block protect register (eeprot) table 7-1. 768-byte eeprom block protection bit name block protected block size bprot4 $0d00 to $0dff 256 bytes bprot3 $0e00 to $0eff 256 bytes bprot2 $0f00 to $0f7f 128 bytes bprot1 $0f80 to $0fbf 64 bytes bprot0 $0fc0 to $0fff 64 bytes address: $00f2 bit 7654321bit 0 read: eeodd eeven marg eecpd eecprd 0 eecpm 0 write: reset:00000000 figure 7-4. eeprom test register (eetst)
eeprom m68hc12b family data sheet, rev. 9.1 96 freescale semiconductor marg ? program and erase voltage margin test enable bit 0 = normal operation 1 = program and erase margin test this bit is used to evaluate the program/erase voltage margin. eecpd ? charge pump disable bit 0 = charge pump is turned on during program/erase. 1 = disable charge pump. eecprd ? charge pump ramp disable bit 0 = charge pump is turned on progressively during program/erase. 1 = disable charge pump controlled ramp up. known to enhance write/erase endurance of eeprom cells. eecpm ? charge pump monitor enable bit 0 = normal operation 1 = output the charge pump voltage on the irq /v pp pin. 7.3.4 eeprom c ontrol register bulkp ? bulk erase protection bit 0 = eeprom can be bulk erased. 1 = eeprom is protected from being bulk or row erased. read anytime. write anytime if eepgm = 0 and protlck = 0. byte ? byte and aligned word erase bit 0 = bulk or row erase is enabled. 1 = one byte or one aligned word erase only read anytime. write anytime if eepgm = 0. row ? row or bulk erase bit (when byte = 0) 0 = erase entire eeprom array. 1 = erase only one 32-byte row. read anytime. write anytime if eepgm = 0. byte and row have no effect when erase = 0. address: $00f3 bit 7654321bit 0 read: bulkp 0 0 byte row erase eelat eepgm write: reset:10000000 figure 7-5. eeprom control register (eeprog) table 7-2. erase selection byte row block size 0 0 bulk erase entire eeprom array 0 1 row erase 32 bytes 1 0 byte or aligned word erase 1 1 byte or aligned word erase
eeprom control registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 97 if byte = 1 and test mode is not enabled, only the lo cation specified by the address written to the programming latches will be erased. the operation will be a byte or an aligned word erase depending on the size of written data. erase ? erase control bit 0 = eeprom configuration for programming or reading 1 = eeprom configuration for erasure read anytime. write anytime if eepgm = 0. configures the eeprom for erasure or programming. when test mode is not enabled and unless bulkp is set, erasure is by byte, aligned word, row, or bulk. eelat ? eeprom latch control bit 0 = eeprom set up for normal reads 1 = eeprom address and data bus latches set up for programming or erasing read anytime. write anytime if eepgm = 0. note when eelat is set, the entire eeprom is unavailable for reads. therefore, no program residing in the eeprom can be executed while attempting to program unused eeprom s pace. care should be taken that no references to the eeprom are used while programming. interrupts should be turned off if the vectors are in the eeprom. timing and any serial communications must be done with polling during the programming process. byte, row, erase, and eelat bits can be wr itten simultaneously or in any sequence. eepgm ? program and erase enable bit 0 = disables program/erase voltage to eeprom 1 = applies program/erase voltage to eeprom the eepgm bit can be set only after eelat has been set. when an attempt is made to set eelat and eepgm simultaneously, eepgm re mains clear but eelat is set. the bulkp, byte, row, erase, and eelat bits c annot be changed when eepgm is set. to complete a program or erase, a write to clear eepgm and eel at bits is required before reading the programmed data. a write to an eeprom loca tion has no effect when eepgm is se t. latched address and data cannot be modified during program or erase. a program or erase operation should follow this sequence: 1. write byte, row, and erase to the desired value; write eelat = 1. 2. write a byte or an aligned word to an eeprom address. 3. write eepgm = 1. 4. wait for programming ( t prog ) or erase ( t erase ) delay time. 5. write eepgm = 0 and eelat = 0. to program/erase more bytes or words without intermediate eeprom reads, only write eepgm = 0 in step 5, leaving eelat = 1, and jump to step 2.
eeprom m68hc12b family data sheet, rev. 9.1 98 freescale semiconductor
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 99 chapter 8 flash eeprom 8.1 introduction the 32-kbyte flash eeprom module for the mc 68hc912b32 and mc68hc 912bc32 serves as electrically erasable and programmable, non-vola tile rom emulation memory. the module can be used for program code that must either execute at high s peed or is frequently executed, such as operating system kernels and standard subroutines, or it can be used for static data which is read frequently. the flash eeprom is ideal for program storage for single-chip applicati ons allowing for field reprogramming. note the mc68hc12be32 and mc68hc12bc32 does not contain flash eeprom. the flash eeprom array is arranged in a 16-bit config uration and may be read as either bytes, aligned words or misaligned words. access time is one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations. the flash eeprom module requires an external program/erase voltage (v fp ) to program or erase the flash eeprom array. the external program/erase voltage is provided to the flash eeprom module via an external v fp pin. to prevent damage to the flash array, v fp should always be greater than or equal to v dd ?0.35 v. programming is by byte or a ligned word. the flash eepr om module supports bulk erase only. the flash eeprom module has hardware interloc ks which protect stored data from accidental corruption. an erase- and program-protected 2-kbyt e block for boot routines is located at $7800?$7fff or $f800?$ffff, depending upon the mapped location of the fl ash eeprom array. (the protected boot block on the initial mask sets, g86w and g75r, is 1-kbyte and is located at $7c00?$7fff or $fc00?$ffff.) 8.2 flash eeprom array after reset, the flash eeprom array is located fr om addresses $8000 to $ffff in single-chip mode. in expanded modes, the flash eeprom array is located from address $0000 to $7fff; however, it is disabled from the memory map. the flash eeprom can be mapped to an al ternate address range. see chapter 5 operating modes and resource mapping . 8.3 flash eeprom registers a 4-byte register block controls the flash eeprom module operation. configuration information is specified and programmed independently from the contents of the flash eeprom array. at reset, the 4-byte register section starts at address $00f4.
flash eeprom m68hc12b family data sheet, rev. 9.1 100 freescale semiconductor 8.3.1 flash eeprom lock control register in normal modes, the lock bit can be written only once after reset. lock ? lock register bit 0 = enable write to feemcr register. 1 = disable write to feemcr register. 8.3.2 flash eepr om module confi guration register this register controls the operation of the fl ash eeprom array. bootp cannot be changed when the lock control bit in the feelck register is set or if enpe in the feectl register is set. the boot block is located at $7800?$7fff or $f800?$ffff, depending upon the mapped location of the flash eeprom array and mask set ($7c00?$ 7fff or $fc00?$ffff for 1-kbyte block). bootp ? boot protect bit 0 = enable erase and program of 1-kbyte or 2-kbyte boot block. 1 = disable erase and program of 1-kbyte or 2-kbyte boot block. 8.3.3 flash eeprom module test register in normal mode, writes to feetst control bits have no effect and always read 0. the flash eeprom module cannot be placed in test mode inadvertently during normal operation. fste ? stress test enable bit 0 = disables the gate/drain stress circuitry 1 = enables the gate/drain stress circuitry address: $00f4 bit 7654321bit 0 read: 0000000lock write: reset:00000000 figure 8-1. flash eeprom lock control register (feelck) address: $00f5 bit 7654321bit 0 read: 0000000bootp write: reset:00000001 figure 8-2. flash eeprom module configuration register (feemcr) address: $00f6 bit 7654321bit 0 read: fste gadr hvt fenlv fdisvfp vtck stre mwpr write: reset:00000000 figure 8-3. flash eeprom module test register (feetst)
flash eeprom registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 101 gadr ? gate/drain stress test select bit 0 = selects the drain stress circuitry 1 = selects the gate stress circuitry hvt ? stress test high voltage status bit 0 = high voltage not present during stress test 1 = high voltage present during stress test fenlv ? enable low voltage bit 0 = disables low voltage transistor in current reference circuit 1 = enables low voltage transistor in current reference circuit fdisvfp ? disable status v fp voltage lock bit when the v fp pin is below normal programming voltage, t he flash module will not allow writing to the lat bit; the user cannot erase or program t he flash module. the fdisvfp control bit enables writing to the lat bit regardless of the voltage on the v fp pin. 0 = enable the automatic lock mechanism if v fp is low. 1 = disable the automatic lock mechanism if v fp is low. vtck ? v t check test enable bit when vtck is set, the flash eeprom module uses the v fp pin to control the control gate voltage; the sense amp timeout path is disabled. this allows for indirect measurements of the bit cells? program and erase threshold. if v fp < v zbrk (breakdown voltage), the control gate will equal the v fp voltage. if v fp > v zbrk , the control gate will be regulated by this equation: control gate voltage = v zbrk + 0.44 (v fp ? v zbrk ) 0 = v t test disable 1 = v t test enable stre ? spare test row enable bit the spare test row consists of one flash eeprom array row. the spare test row is reserved and contains production test information which must be maintained through several erase cycles. when stre is set, the decoding for the spare test row ov errides the address lines wh ich normally select the other rows in the array. 0 = lib accesses are to the flash eeprom array. 1 = spare test row in array enabled if smod is active mwpr ? multiple word programming bit used primarily for testing, if mpwr = 1, the tw o least significant address lines, addr1 and addr0, will be ignored when programmi ng a flash eeprom location. the word location addressed if addr1 and addr0 = 00, along with the word loca tion addressed if addr1 and addr0 = 10, will both be programmed with the same word data from the programming latches. this bit should not be changed during programming. 0 = multiple word programming disabled 1 = program 32 bits of data
flash eeprom m68hc12b family data sheet, rev. 9.1 102 freescale semiconductor 8.3.4 flash eeprom control register this register controls the program ming and erasure of the flash eeprom. feeswai ? flash eeprom stop in wait control bit 0 = do not halt flash eeprom clock when in wait mode. 1 = halt flash eeprom cl ock when in wait mode. note the feeswai bit cannot be asserted if the interrupt vector resides in the flash eeprom array. svfp ? status v fp voltage bit svfp is a read-only bit. 0 = voltage of v fp pin is below normal programming voltage levels. 1 = voltage of v fp pin is above normal programming voltage levels. eras ? erase control bit this bit can be read anytime or written when enpe = 0. when set, all locations in the array will be erased at the same time. the boot block will be erased only if bootp = 0. this bit also affects the result of attempted array reads. see table 8-1 for more information. status of eras cannot change if enpe is set. 0 = flash eeprom configured for programming 1 = flash eeprom configured for erasure lat ? latch control bit this bit can be read anytime or written when en pe = 0. when set, the flash eeprom is configured for programming or erasure and, upon the next valid wr ite to the array, the address and data will be latched for the programming sequence. see table 8-1 for the effects of lat on array reads. a high voltage detect circuit on the v fp pin will prevent assertion of the lat bit when the programming voltage is at normal levels. 0 = programming latches disabled 1 = programming latches enabled enpe ? enable programming/erase bit 0 = disables program/erase voltage to flash eeprom 1 = applies program/erase voltage to flash eeprom enpe can be asserted only after lat has been as serted and a write to the data and address latches has occurred. if an attempt is made to assert enpe when lat is negated, or if the latches have not been written to after lat was asserted, enpe will remain negated after the write cycle is complete. the lat, eras, and bootp bits cannot be changed when enpe is asserted. a write to feectl may affect only the state of enpe. attempts to re ad a flash eeprom array location in the flash eeprom module while enpe is asserted will not return the data addressed. see table 8-1 for more information. address: $00f7 bit 7654321bit 0 read: 0 0 0 feeswai svfp eras lat enpe write: reset:00000000 figure 8-4. flash eeprom control register (feectl)
operation m68hc12b family data sheet, rev. 9.1 freescale semiconductor 103 flash eeprom module control registers may be r ead or written while enpe is asserted. if enpe is asserted and lat is negated on the same write ac cess, no programming or erasure will be performed. 8.4 operation the flash eeprom can contain program and data. on reset, it can oper ate as a bootstrap memory to provide the cpu with internal initialization information during the reset sequence. 8.4.1 bootstrap oper ation single-chip mode after reset, the cpu controlling the sy stem will begin booting up by fetchi ng the first program address from address $fffe. 8.4.2 normal operation the flash eeprom allows a byte or aligned word read/write in one bus cycle. misaligned word read/write require an additional bus cycle. the fl ash eeprom array responds to read operations only. write operations are ignored. 8.4.3 program/erase operation an unprogrammed flash eeprom bit has a logic state of 1. a bit must be programmed to change its state from 1 to 0. erasing a bit returns it to a logic 1. the flash eeprom has a minimum program/erase life of 100 cycles. programming or erasing the flash eeprom is accomplished by a series of control register writes and a write to a set of programming latches. programming is restricted to a single byte or aligned word at a time determined by internal signals sz8 and addr0. the flash eeprom must first be comple tely erased prior to programming final data values. it is possible to program a location in the flash eeprom without erasing the entire array, if the new value does not require the changing of bit values from 0 to 1. 8.4.3.1 read/write accesses during program/erase during program or erase operations, read and write accesses may be different from those during normal operation and are affected by the state of the co ntrol bits in the flash eeprom control register (feectl). the next write to any valid address to t he array after lat is set will cause the address and data to be latched into the programming latches. once the address and data are latched, write accesses to the array will be ignored while lat is set. writ es to the control registers will occur normally. table 8-1. effects of enpe, lat, and eras on array reads enpe lat eras result of read 0 0 ? normal read of location addressed 0 1 0 read of location being programmed 0 1 1 normal read of location addressed 1 ? ? read cycle is ignored
flash eeprom m68hc12b family data sheet, rev. 9.1 104 freescale semiconductor 8.4.3.2 program/erase verification when programming or erasing the flash eeprom arra y, a special verificati on method is required to ensure that the program/erase process is reliable and also to provide the longes t possible life expectancy. this method requires stopping the program/erase sequence at periods of t ppulse (t epulse for erasing) to determine if the flash eeprom is programmed/er ased. after the location reaches the proper value, it must continue to be programmed/erased with additional margin pulses to ensure that it will remain programmed/erased. failure to provide the margin pu lses could lead to corrupted or unreliable data. 8.4.3.3 program/erase sequence to begin a program or erase sequence, the external v fp voltage must be applied and stabilized. the eras bit must be set or cleared, depending on whether a program sequence or an erase sequence is to occur. the lat bit will be set to cause any subsequent data written to a valid address within the flash eeprom to be latched into the programming address and data latches. the next flash array write cycle must be either to the location that is to be progr ammed if a programming sequence is being performed, or, if erasing, to any valid flash eeprom array lo cation. writing the new add ress and data information to the flash eeprom is followed by assertion of enpe to turn on the program/erase voltage to program/erase the new location(s). the lat bit must be asserted and the address and data latched to allow the setting of the enpe control bit. if the data and address have not been latched, an attempt to assert enpe will be ignored and enpe will remain negat ed after the write cycle to feectl is completed. the lat bit must remain asserted and the eras bit must remain in its current state as long as enpe is asserted. a write to the lat bit to clear it while enpe is set will be ignored. that is, after the write cycle, lat will remain asserted. likewise, an attempt to change the state of eras will be ignored and the state of the eras bit will remain unchanged. the programming software is responsible for all timing during a program sequence. this includes the total number of program pulses (n pp ), the length of the program pulse (t ppulse ), the program margin pulses (p m ) and the delay between turning off the high voltage and verifying the operation (t vprog ). the erase software is responsible for all timing duri ng an erase sequence. this includes the total number of erase pulses (e m ), the length of the erase pulse (t epulse ), the erase margin pulse or pulses, and the delay between turning off the high voltage and verifying the operation (t verase ). software also controls the supply of the proper program/erase voltage to the v fp pin and should be at the proper level before enpe is set during a program/erase sequence. a program/erase cycle should not be in progress when starting another program/erase or while attempting to read from the array. note although clearing enpe disables the program/erase voltage (v fp ) from the v fp pin to the array, care must be taken to ensure that v fp is at v dd whenever programming/erasing is not in progress. not doing so could damage the part. ensuring that v fp is always greater or equal to v dd can be accomplished by controlling the v fp power supply with the programming software via an output pin. alternativ ely, all programming and erasing can be done prior to installing the device on an application circuit board which can always connect v fp to v dd . programming can also be accomplished by plugging the board into a specia l programming fixture which provides program/erase voltage to the v fp pin.
programming the flash eeprom m68hc12b family data sheet, rev. 9.1 freescale semiconductor 105 8.5 programming the flash eeprom programming the flash eeprom is accomplished by this st ep-by-step procedure. the v fp pin voltage must be at the proper level prior to executing step 4 the first time. 1. apply program/erase voltage to the v fp pin. 2. clear eras and set the lat bit in the feectl register to establish program mode and enable programming address and data latches. 3. write data to a valid address. the address and dat a are latched. if bootp is asserted, an attempt to program an address in the boot block will be ignored. 4. apply programming voltage by setting enpe. 5. delay for one programming pulse, t ppulse . 6. remove programming voltage by clearing enpe. 7. delay while high voltage is turning off, t vprog . 8. read the address location to verify that it has been programmed, 9. if the location is not programmed, repeat steps 4 through 7 until the location is programmed or until the specified maximum number of program pulses, n pp , has been reached. 10. if the location is programmed, repeat the same number of pulses as required to program the location. this provides 100 percent program margin. 11. read the address location to verify that it remains programmed. 12. clear lat. 13. if there are more locations to program, repeat steps 2 through 10. 14. turn off v fp . reduce voltage on v fp pin to v dd . the flowchart in figure 8-5 demonstrates the recommended programming sequence.
flash eeprom m68hc12b family data sheet, rev. 9.1 106 freescale semiconductor figure 8-5. program sequence flow start prog set lat clear eras write data to address set enpe read get next address/data no location failed location clear margin flag increment n pp counter no decrement n pp counter no yes yes yes to program turn on v fp delay for duration of program pulse (t ppulse ) clear enpe delay before verify is margin flag set? no yes no yes data correct? set margin flag data correct? n pp = 0? done? turn off v fp (t vprog ) n pp = 50? yes no done prog clear program pulse counter (n pp ) clear lat
erasing the flash eeprom m68hc12b family data sheet, rev. 9.1 freescale semiconductor 107 8.6 erasing the flash eeprom this sequence demonstrates the recommended procedure for erasing the flash eeprom. the v fp pin voltage must be at the proper level prior to executing step 4 the first time. 1. turn on v fp . apply program/erase voltage to the v fp pin. 2. set the lat bit and eras bit to conf igure the flash eeprom for erasing. 3. write to any valid address in the flash array. this allows the erase voltage to be turned on; the data written and the address written are not import ant. the boot block will be erased only if the control bit bootp is negated. 4. apply erase voltage by setting enpe. 5. delay for a single erase pulse, t epulse . 6. remove erase voltage by clearing enpe. 7. delay while high voltage is turning off, t verase . 8. read the entire arra y to ensure that the flash eeprom is erased. 9. if all of the flash eeprom locations are not er ased, repeat steps 4 thr ough 7 until either the remaining locations are erased or until the maximum erase pulses have been applied, n ep . 10. if all of the flash eeprom locations are erased, repeat the same number of pulses as required to erase the array. this provides 100 percent erase margin. 11. read the entire arra y to ensure that the flash eeprom is erased. 12. clear lat. 13. turn off v fp . reduce voltage on v fp pin to v dd . the flowchart in figure 8-6 demonstrates the recommended erase sequence.
flash eeprom m68hc12b family data sheet, rev. 9.1 108 freescale semiconductor figure 8-6. erase sequence flow start erase set lat set eras write to array set enpe read no array failed to erase array clear margin flag increment n ep counter decrement n ep counter no yes yes turn on v fp delay for duration of erase pulse (t epulse ) clear enpe delay before verify is margin flag set? no yes no yes array erased? set margin flag n ep = 0? turn off v fp (t verase ) n ep = 5? yes no array erased clear erase pulse counter (n ep ) clear lat array erased?
program/erase protection interlocks m68hc12b family data sheet, rev. 9.1 freescale semiconductor 109 8.7 program/erase protection interlocks the flash eeprom program and erase mechanisms provide maximum protec tion from accidental programming or erasure. the voltage required to program/erase the flash eeprom (v fp ) is supplied via an external pin. if v fp is not present, no programming/erasing will occur. furthermore, the program/erase voltage will not be applied to the flash eeprom unless turned on by setting a control bit (enpe). the enpe bit may not be set unless the programming address and data latc hes have been written prev iously with a valid address. the latches may not be written unless enabled by setting a control bit (lat). the lat and enpe control bits must be written on separate writes to the control register (feectl) and must be separated by a write to the programming latches. the eras and lat bits are also protected when enpe is set. this prevents inadvertent switching between erase/program mode and also prevents the latched data and address from being changed after a program cycle has been initiated. 8.8 stop or wait mode when stop or wait commands ar e executed, the mcu puts the flash eeprom in stop or wait mode. in these modes, the flash module will c ease erasure or programming immediately. note it is advised to not enter stop or wait modes when programming the flash array. the flash eeprom module is not able to recover from stop mode without a 250-ns delay. if the operating bus frequency is greater than 4 mhz, the dly bit must be set to1 to use the flash after recovering from stop mode. other options are to map the eeprom module over the flash module in the memory map with dly = 0 and place the interrupt vectors in the eeprom array or use reset to reco ver from a stop mode executed from flash eeprom. recovery from a st op instruction executed from eeprom and ram operates normally. 8.9 test mode the flash eeprom has some special test functions which are only accessible when the device is in test mode. test mode is indicated to the flash eeprom module when the smod line on the lib is asserted. when smod is asserted, the special test c ontrol bits may be accessed via the lib to invoke the special test functions in the flash eeprom module. when smod is not asserted, writes to the test control bits have no effect and all bits in the test register feetst will be cleared. this ensures that flash eeprom test mode cannot be invoked inadvertently during normal operation. the flash eeprom module will operate normally, even if smod is as serted, until a special test function is invoked. the test mode adds additional features over normal mode. these features allow the tests to be performed even after the device is installed in the final product.
flash eeprom m68hc12b family data sheet, rev. 9.1 110 freescale semiconductor
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 111 chapter 9 read-only memory (rom) 9.1 introduction the mc68hc12be32 and mc68hc12bc32 contain 32 kbytes of read-only memory (rom). the rom array is arranged in a 16-bit configuration and may be read as either bytes, aligned words or misaligned words. access time is one bus cycle for byte and al igned word access and two bus cycles for misaligned word operations. 9.2 rom array after reset, the rom array is located from addresses $8000 to $ffff in single-chip mode. in expanded modes, the rom array is located from address $0000 to $7fff; however, it is disabled from the memory map. the rom can be mapped to an alternate address range. see chapter 5 operating modes and resource mapping .
read-only memory (rom) m68hc12b family data sheet, rev. 9.1 112 freescale semiconductor
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 113 chapter 10 clock generation module (cgm) 10.1 introduction the clock generation module (cgm) gen erates the system clocks and generates and controls the timing of the reset and power-on reset (por) logic. the cgm is composed of: clock selection and generation circuitry slow-mode clock divider reset and stop generation timing and control note older device mask sets do not support the slow-mode clock divider feature. register $00e0 is reserved in ol der devices and provides no function. mask sets that do not have the slow -mode clock divider feature on the mc68hc912b32 include: g96p, g86w, and h91f. mask sets that do not have the slow -mode clock divider feature on the mc68hc12be32 include: h54t and j38m. mask sets that do not have the slow -mode clock divider feature on the mc68hc(9)12bc32 include: j15g. 10.2 block diagram figure 10-1. cgm block diagram extal xtal e clock p clock t clock reduced consumption oscillator t clock generator to cpu slow mode clock divider wait slow e clock oscillator 2 e and p clock generator to bdlc and tim e clock (gbt) p clock (gbt) to buses, bdm, spi, sci, atd, rti, cop, pwm, fee, ee, ram slow p clock out
clock generation module (cgm) m68hc12b family data sheet, rev. 9.1 114 freescale semiconductor 10.3 register map 10.4 clock selection and generation the cgm generates the p clock, the e clock, and four t clocks. the p clock and e clock are used by all device modules except the cpu. the t clocks are used by the cpu. figure 10-3 shows clock timing relationships while in normal run modes. there are two types of p clocks and e clocks while in wait mode: global type (g), which is driven by the slow cl ock divider in wait mode and drives all on-chip peripherals except the bdlc and the timer global type (gbt), which remains at the oscillator divide-by-2 rate in wait mode and drives the bdlc and the timer figure 10-4 shows clock timing relationships while in wait mode. addr. register name bit 7654321bit 0 $0014 real-time interrupt control register (rtictl) see page 118. read: rtie rswai rsbck 0 rtbyp rtr2 rtr1 rtr0 write: reset:00000000 $0015 real-time interrupt flag register (rtiflg) see page 119. read: rtif0000000 write: reset:00000000 $0016 cop control register (copctl) see page 119. read: cme fcme fcm fcop disr cr2 cr1 cr0 write: reset:00000001 $0017 arm/reset cop timer register (coprst) see page 120. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00e0 slow mode divider register (slow) see page 117. read: 0 0 0 0 0 sldv2 sldv1 sldv0 write: reset:00000000 = unimplemented figure 10-2. cgm register map
clock selection and generation m68hc12b family data sheet, rev. 9.1 freescale semiconductor 115 figure 10-3. internal clock relationships in normal run modes figure 10-4. internal clock relationships in wait mode t1 clock t2 clock t3 clock t4 clock e clock p clock oscillator e clock p clock oscillator t1 clock t2 clock t3 clock t4 clock e clock p clock 1. driven by slow clock divider in wait mode. drives on-chip per ipherals except bdlc and timer. 2. remains at oscillator divided by 2 ra te in wait mode. drives bdlc and timer. notes: (g) (1) (g) (1) (gbt) (2) (gbt) (2)
clock generation module (cgm) m68hc12b family data sheet, rev. 9.1 116 freescale semiconductor 10.5 slow mode divider the slow mode divider is included to deliver a vari able bus frequency to the mcu in wait mode. the bus clocks are derived from the constant p clock. th e slow clock counter divides the p clock and e clock frequency in powers of 2, up to 128. when the slow cont rol register is cleared or the part is not in wait mode, the slow mode divider is off and the bus clock?s frequency is not changed. note the clock monitor is clocked by the sys tem clock (oscillator) reference; the slow mode divider allows operation of t he mcu at clock periods longer than the clock monitor trigger time. 10.6 clock functions the cgm generates and controls the timing of the reset and por logic. 10.6.1 computer oper ating properly (cop) the computer operating properly (cop) or watchdog ti mer is an added check that a program is running and sequencing properly. when the cop is being used, so ftware is responsible for keeping a free-running watchdog timer from timing out. if the watchdog timer time s out, it is an indication that the software is no longer being executed in the intended sequence; thus, a system reset is initiated. three control bits allow selection of seven cop timeout periods or cop di sable. when cop is enabled, sometime during the selected period the program must write $55 and $aa (in this order) to the arm/reset cop register (coprst). if the program fails to do this, the part resets. if any value other than $55 or $aa is written to coprst, the part is reset. 10.6.2 real-time interrupt there is a real-time (periodic) interr upt available to the user. this interrupt occurs at one of seven selected rates. an interrupt flag and an interrupt enable bit are associated with this function. there are three bits for the rate select. 10.6.3 clock monitor the clock monitor circuit is based on an internal resi stor-capacitor (rc) time delay. if no mcu clock edges are detected within this rc time delay, the clo ck monitor can optionally generate a system reset. the clock monitor function is enabled/d isabled by the cme control bit in the cop control register (copctl). this timeout is based on an rc delay so that the clock monitor can operate without any mcu clocks. clock monitor timeouts are shown in table 10-1 . table 10-1. clock monitor timeout supply range 5 v 10 % 2?20 s
clock registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 117 10.7 clock registers this section describes the clock registers. all regist er addresses shown reflect the reset state. registers may be mapped to any 2-kbyte space. 10.7.1 slow mode divider register sldv2?sldv0 ? slow mode divisor selector bits the value 2 raised to the power indicated by t hese three bits produces the slow mode frequency divider. the range of the divider is 2 to 128 by steps of power of 2. when the bits are clear, the divider is bypassed. table 10-2 shows the divider for all bit conditions and the resulting bus rate for three example oscillator frequencies. address: $00e0 bit 7654321bit 0 read:00000 sldv2 sldv1 sldv0 write: reset:00000000 = unimplemented figure 10-5. slow mode divider register (slow) table 10-2. slow mode register divider rates sldv2 sldv1 sldv0 divider (2 x ) bus rate (16-mhz oscillator) bus rate (8-mhz oscillator) bus rate (4-mhz oscillator) 0 0 0 off 8 mhz 4 mhz 2 mhz 0 0 1 2 4 mhz 2 mhz 1 mhz 0 1 0 4 2 mhz 1 mhz 500 khz 0 1 1 8 1 mhz 500 khz 250 khz 1 0 0 16 500 khz 250 khz 125 khz 1 0 1 32 250 khz 125 khz 62.5 khz 1 1 0 64 125 khz 62.5 khz 31.2 khz 1 1 1 128 62.5 khz 31.2 khz 15.6 khz
clock generation module (cgm) m68hc12b family data sheet, rev. 9.1 118 freescale semiconductor 10.7.2 real-time inte rrupt control register read: anytime write: varies on a bit-by-bit basis rtie ? real-time interrupt enable bit write anytime. 0 = interrupt requests from rti are disabled. 1 = interrupt is requested when rti is set. rswai ? rti and cop stop while in wait bit write once in normal modes, anytime in special modes. 0 = allows the rti and cop to continue running in wait 1 = disables both the rti and cop when the part goes into wait rsbck ? rti and cop stop while in background debug mode bit write once in normal modes, anytime in special modes. 0 = allows the rti and cop to continue running while in background mode 1 = disables rti and cop when the part is in background mode (useful for emulation) rtbyp ? real-time interrupt divider chain bypass bit write is not allowed in normal modes, anytime in special modes. 0 = divider chain functions normally. 1 = divider chain is bypas sed, allows faster testing. the divi der chain is normally p divided by 2 13 , when bypass becomes p divided by 4. rtr2, rtr1, and rtr0 ? real-time interrupt rate select bits write anytime. rate select for real-time interrupt. the e clock is used for this module. address: $0014 bit 7654321bit 0 read: rtie rswai rsbck 0 rtbyp rtr2 rtr1 rtr0 write: reset:00000000 = unimplemented figure 10-6. real-time interrupt control register (rtictl) table 10-3. real-time interrupt rates rtr2 rtr1 rtr0 divide e by: timeout period e = 4.0 mhz timeout period e = 8.0 mhz 000 off off off 001 2 13 2.048 ms 1.024 ms 010 2 14 4.096 ms 2.048 ms 011 2 15 8.196 ms 4.096 ms 100 2 16 16.384 ms 8.196 ms 101 2 17 32.768 ms 16.384 ms 110 2 18 65.536 ms 32.768 ms 111 2 19 131.72 ms 65.536 ms
clock registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 119 10.7.3 real-time in terrupt flag register rtif ? real-time interrupt flag bit this bit is cleared automatically by a wr ite to this register with this bit set. 0 = timeout has not yet occurred. 1 = set when the timeout period is met 10.7.4 cop control register read: anytime write: varies on a bit by bit basis cme ? clock monitor enable bit write anytime. if fcme is set, this bit has no meaning or effect. 0 = clock monitor is disabled; slow clocks and stop instruction may be used. 1 = slow or stopped clocks (including the st op instruction) cause a clock reset sequence. fcme ? force clock monitor enable bit write once in normal modes, anytime in special modes. in normal modes, when this bit is set, the clock moni tor function cannot be disabled until a reset occurs. 0 = clock monitor follows the state of the cme bit. 1 = slow or stopped clocks cause a clock reset sequence. to use both stop and clock monitor, the cme bit should be cleared prior to executing a stop instruction and set after recovery from stop. al ways keep fcme = 0, if stop will be used. fcm ? force clock monitor reset bit writes are not allowed in normal modes, anytime in special modes. if disr is set, this bit has no effect. 0 = normal operation 1 = force a clock monitor reset, if clock monitor is enabled. address: $0015 bit 7654321bit 0 read: rtif0000000 write: reset:00000000 figure 10-7. real-time interrupt flag register (rtiflg) address: $0016 bit 7654321bit 0 read: cme fcme fcm fcop disr cr2 cr1 cr0 write: normal reset:00000001 special reset:00001001 figure 10-8. cop control register (copctl)
clock generation module (cgm) m68hc12b family data sheet, rev. 9.1 120 freescale semiconductor fcop ? force cop watchdog reset bit writes are not allowed in normal modes; can be written anytime in special modes. if disr is set, this bit has no effect. 0 = normal operation 1 = force a cop reset, if cop is enabled. disr ? disable resets from cop watchdog and clock monitor bit writes are not allowed in normal modes, anytime in special modes. 0 = normal operation 1 = regardless of other control bit states, cop and clock monitor do not generate a system reset. cr2, cr1, and cr0 ? cop watchdog timer rate select bit the cop system is driven by a constant frequency of e/2 13 . (rtbyp in the rtictl register allows all but two stages of this divider to be bypassed for te sting in special modes only.) these bits specify an additional division factor to arrive at the cop time out rate. the clock used for this module is the e clock. write once in normal modes, anytime in special modes. 10.7.5 arm/reset cop timer register always reads $00. writing $55 to this address is the first step of the cop watchdog sequence. writing $aa to this address is the second step of the cop watchdog sequence. other instructions may be executed between these writes but both must be completed in the correct order prior to timeout to avoid a watchdog reset. writing anything other t han $55 or $aa causes a cop reset to occur. table 10-4. cop watchdog rates (rtbyp = 0) cr2 cr1 cr0 divide e by: at e = 4.0-mhz timeout 0 to +2.048 ms at e = 8.0-mhz timeout 0 to +1.024 ms 0 0 0 off off off 001 2 13 2.048 ms 1.024 ms 010 2 15 8.1920 ms 4.096 ms 011 2 17 32.768 ms 16.384 ms 100 2 19 131.072 ms 65.536 ms 101 2 21 524.288 ms 262.144 ms 110 2 22 1.048 s 524.288 ms 111 2 23 2.097 s 1.048576 s address: $0017 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 10-9. arm/reset cop timer register (coprst)
clock divider chains m68hc12b family data sheet, rev. 9.1 freescale semiconductor 121 10.8 clock divider chains figure 10-10 , figure 10-11 , figure 10-12 , and figure 10-13 summarize the clock divider chains for these peripherals: sci ? serial peripheral interface bdlc ? byte data link communications rti ? real-time interrupt cop ? computer operating properly tim ? standard timer module ect ? enhanced capture timer spi ? serial peripheral interface atd ? analog-to-digital converter bdm ? background debug mode figure 10-10. clock chain for sci, bdlc, rti, and cop p clock bits: rtr2, rtr1, and rtr0 bits: cr2, cr1, and cr0 2 4 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 2 2 2 2 2 2 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 4 4 4 2 4 2 register: copctl register: rtictl 2 11 2 2 bit: rtbyp register: rtictl 0:0 0:1 1:0 1:1 2 2 2 bits: r1, r0 register: bcr1 to bdlc to rti to cop sc0bd modulus divider: 1, 2, 3, 4, 5, 6, ..., 8190, 8191 sci0 receive baud rate (16x) sci0 transmit baud rate (1x)
clock generation module (cgm) m68hc12b family data sheet, rev. 9.1 122 freescale semiconductor figure 10-11. clock chain for tim figure 10-12. clock chain for ect bits: pr2, pr1, and pr0 p clock 1:0:0 1:0:1 1:1:0 1:1:1 port t7 pamod paclk paclk/256 paclk/65536 (paov) gate logic bits: paen, clk1, and clk0 0:x:x ten paen 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 2 2 2 2 2 2 register: pactl register: tmsk2 pulse acc high byte to tim counter pulse acc low byte bits: pr2, pr1, and pr0 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 2 2 2 2 2 2 0:x:x 1:0:0 1:0:1 1:1:0 1:1:1 register: tmsk2 0:0 0:1 1:0 1:1 2 4 2 bits: mcpr1 and mcpr0 register: mcctl 2 ten mclk mcen modulus down gate logic to timer main counter pulse acc high byte paclk/65536 (paov) paclk/256 pulse acc low byte bits: paen, clk1, and clk0 register: pactl port t7 paen pamod paclk
clock divider chains m68hc12b family data sheet, rev. 9.1 freescale semiconductor 123 figure 10-13. clock chain for spi, atd, and bdm p clock bits : spr2, spr1, and spr0 e clock bkgd bdm bit clock: receive: detect falling edge, count 12 e clocks, sample input transmit 1: detect falling edge, count 6 e clocks while output is high impedance, drive out 1 e cycle pulse high, high-impedance output again transmit 0: detect falling edge, drive out low, count 9 e clocks, drive out 1 e cycle pulse high, high-impedance output pin synchronizer logic 2 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 2 2 2 2 2 2 2 2 register: sp0br to atd spi bit rate 5-bit modulus counter (pr0-pr4) bkgd in bkgd out bkgd direction
clock generation module (cgm) m68hc12b family data sheet, rev. 9.1 124 freescale semiconductor
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 125 chapter 11 pulse-width modulator (pwm) 11.1 introduction the pulse-width modulator (pwm) subsystem provi des four independent 8-bit pwm waveforms or two 16-bit pwm waveforms or a combination of one 16-bit and two 8-bit pwm waveforms. each waveform channel has a programmable period an d a programmable duty cycle as we ll as a dedicated counter. a flexible clock select scheme allows four different clock sources to be used with the counters. each of the modulators can create independent, continuous wavefo rms with software-selectable duty rates from 0 percent to 100 percent. the pwm outputs can be pr ogrammed as left-aligned outputs or center-aligned outputs. see figure 11-1 , figure 11-2 , and figure 11-3 . the period and duty registers are double buffered so th at if they change while the channel is enabled, the change does not take effect until t he counter rolls over or the channel is disabled. if the channel is not enabled, then writes to the period and/or duty register go directly to the latches as well as the buffer, thus ensuring that the pwm output is always either the old waveform or the new waveform, not some variation in between. a change in duty or period can be forced into immediat e effect by writing the new value to the duty and/or period registers and then writing to the counter. this causes the counter to reset and the new duty and/or period values to be latched. in addition, since the c ounter is readable it is possible to know where the count is with respect to the duty value and software can be used to make adjustments by turning the enable bit off and on. the four pwm channel outputs share general-purpos e port p pins. enabling pwm pins takes precedence over the general-purpose port. when pwm outputs are not in use, the port pins may be used for discrete input/output.
pulse-width modulator (pwm) m68hc12b family data sheet, rev. 9.1 126 freescale semiconductor figure 11-1. block diagram of pwm left-aligned output channel figure 11-2. block diagram of pwm center-aligned output channel gate pwcntx 8-bit compare pwdtyx 8-bit compare = pwperx up counter only from port p data register to pin driver ppolx clock source (eclk) clock edge sync reset centr = 0 mux mux s r q q pwper pwdty pwenx ppol = 0 ppol = 1 gate pwcntx 8-bit compare pwdtyx 8-bit compare = pwperx reset from port p data register to pin driver ppolx clock source (eclk) clock edge sync centr = 1 mux mux t q q pwdty pwenx ppol = 0 ppol = 1 duty cycle period pwper 2 (pwper ? pwdty) 2 pwdty up /down counter with reset upon enable
introduction m68hc12b family data sheet, rev. 9.1 freescale semiconductor 127 figure 11-3. pwm clock sources 8-bit down counter pclk2 mux pclk3 mux clock to pwm channel 2 clock to pwm channel 3 2 pwscnt1 8-bit scale register pwscal1 clock b clock s1** **clock s1 = (clock b)/2, (clock b)/4, (clock b)/6,... (clock b)/512 2 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 2 2 2 2 2 2 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 8-bit down counter pclk0 mux pclk1 mux clock to pwm channel 0 clock to pwm channel 1 2 pwscnt0 8-bit scale register pwscal0 clock a clock s0* *clock s0 = (clock a)/2, (clock a)/4, (clock a)/6,... (clock a)/512 register: bits: pckb2, pckb0 pckb1, = 0 = 0 bits: pcka2, pcka0 pcka1, pwpres psbck limbdm eclk psbck is bit 0 of pwctl register. internal signal limbdm is 1 if the mcu is in background debug mode.
pulse-width modulator (pwm) m68hc12b family data sheet, rev. 9.1 128 freescale semiconductor 11.2 pwm register descriptions this section provides descriptions of the pwm registers. 11.2.1 pwm clocks and c oncatenate register read: anytime write: anytime con23 ? concatenate pwm channels 2 and 3 bit when concatenated, channel 2 becomes the high-or der byte and channel 3 becomes the low-order byte. channel 2 output pin is used as the output for this 16-bit pwm (bit 2 of port p). channel 3 clock-select control bits determines the clock source. 0 = channels 2 and 3 are separate 8-bit pwms. 1 = channels 2 and 3 are concatenated to create one 16-bit pwm channel. con01 ? concatenate pwm channels 0 and 1 bit when concatenated, channel 0 becomes the high-or der byte and channel 1 becomes the low-order byte. channel 0 output pin is used as the output for this 16-bit pwm (bit 0 of port p). channel 1 clock-select control bits determine the clock source. 0 = channels 0 and 1 are separate 8-bit pwms. 1 = channels 0 and 1 are concatenated to create one 16-bit pwm channel. pcka2?pcka0 ? prescaler for clock a bits clock a is one of two clock sources which may be used for channels 0 and 1. these three bits determine the rate of clock a, as shown in table 11-1 . pckb2?pckb0 ? prescaler for clock b bits clock b is one of two clock sources which may be used for channels 2 and 3. these three bits determine the rate of clock b, as shown in table 11-1 . address: $0040 bit 7654321bit 0 read: con23 con01 pcka2 pcka1 pcka0 pckb2 pckb1 pckb0 write: reset:00000000 figure 11-4. pwm clocks and concatenate register (pwclk) table 11-1. clock a and clock b prescaler pcka2 (pckb2) pcka1 (pckb1) pcka0 (pckb0) value of clock a (b) 000 e 001 e 2 010 e 4 011 e 8 100e 16 101e 32 110e 64 111e 128
pwm register descriptions m68hc12b family data sheet, rev. 9.1 freescale semiconductor 129 11.2.2 pwm clock select and polarity register read: anytime write: anytime pclk3 ? pwm channel 3 clock select bit 0 = clock b is the clock source for channel 3. 1 = clock s1 is the clock source for channel 3. pclk2 ? pwm channel 2 clock select bit 0 = clock b is the clock source for channel 2. 1 = clock s1 is the clock source for channel 2. pclk1 ? pwm channel 1 clock select bit 0 = clock a is the clock source for channel 1. 1 = clock s0 is the clock source for channel 1. pclk0 ? pwm channel 0 clock select bit 0 = clock a is the clock source for channel 0. 1 = clock s0 is the clock source for channel 0. if a clock select is changed while a pwm signal is being generated, a truncated or stretched pulse may occur during the transition. ppol3 ? pwm channel 3 polarity bit 0 = channel 3 output is low at the beginning of the period, high when the duty count is reached. 1 = channel 3 output is high at the beginning of the period, low when the duty count is reached. ppol2 ? pwm channel 2 polarity bit 0 = channel 2 output is low at the beginning of the period, high when the duty count is reached. 1 = channel 2 output is high at the beginning of the period, low when the duty count is reached. ppol1 ? pwm channel 1 polarity bit 0 = channel 1 output is low at the beginning of the period, high when the duty count is reached. 1 = channel 1 output is high at the beginning of the period, low when the duty count is reached. ppol0 ? pwm channel 0 polarity bit 0 = channel 0 output is low at the beginning of the period, high when the duty count is reached. 1 = channel 0 output is high at the beginning of the period, low when the duty count is reached. depending on the polarity bit, the duty registers may cont ain the count of either the high time or the low time. if the polarity bit is 0 and left alignment is selected, the duty registers contain a count of the low time. if the polarity bit is 1, the duty registers contain a count of the high time. address: $0041 bit 7654321bit 0 read: pclk3 pclk2 pclk1 pcl k0 ppol3 ppol2 ppol1 ppol0 write: reset:00000000 figure 11-5. pwm clock select and polarity register (pwpol)
pulse-width modulator (pwm) m68hc12b family data sheet, rev. 9.1 130 freescale semiconductor 11.2.3 pwm enable register read: anytime write: anytime setting any of the pwenx bits causes the associated port p line to become an output regardless of the state of the associated data direction register (ddrp) bit. this does not change the state of the data direction bit. when pwenx returns to 0, the data directi on bit controls i/o direction. on the front end of the pwm channel, the scaler clock is enabled to th e pwm circuit by the pwenx enable bit being high. when all four pwm channels are dis abled, the prescaler counter shuts off to save power. there is an edge-synchronizing gate circuit to guarantee that the clock is only enabled or disabled at an edge. pwen3 ? pwm channel 3 enable bit the pulse modulated signal will be available at port p bit 3 when its clock sour ce begins its next cycle. 0 = channel 3 disabled 1 = channel 3 enabled pwen2 ? pwm channel 2 enable bit the pulse modulated signal will be available at port p bit 2 when its clock sour ce begins its next cycle. 0 = channel 2 disabled 1 = channel 2 enabled pwen1 ? pwm channel 1 enable bit the pulse modulated signal will be available at port p bit 1 when its clock source begins its next cycle. 0 = channel 1 disabled 1 = channel 1 enabled pwen0 ? pwm channel 0 enable bit the pulse modulated signal will be available at port p bit 0 when its clock sour ce begins its next cycle. 0 = channel 0 disabled 1 = channel 0 enabled address: $0042 bit 7654321bit 0 read:0000 pwen3 pwen2 pwen1 pwen0 write: reset:00000000 = unimplemented figure 11-6. pwm enable register (pwen)
pwm register descriptions m68hc12b family data sheet, rev. 9.1 freescale semiconductor 131 11.2.4 pwm prescale counter read: anytime write: only in special mode (smod = 1) pwpres is a free-running 7-bit counter. 11.2.5 pwm scale register 0 read: anytime write: anytime a write causes the scaler counter pwscnt0 to load t he pwscal0 value unless it is in special mode with discal = 1 in the pwtst register. pwm channels 0 and 1 can select clock s0 (scaled) as its input clock by setting the control bit pclk0 and pclk1 respectively. clock s0 is generated by dividing clock a by the value in the pwscal0 register plus one and dividing again by two. when pwscal0 = $ ff, clock a is divided by 256 then divided by two to generate clock s0. 11.2.6 pwm scale counter 0 value read: anytime pwscnt0 is a down-counter that, upon reaching $00, loads the value of pwscal0. address: $0043 bit 7654321bit 0 read: 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 11-7. pwm prescale counter (pwpres) address: $0044 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 11-8. pwm scale register 0 (pwscal0) address: $0045 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 11-9. pwm scale counter register 0 (pwscnt0)
pulse-width modulator (pwm) m68hc12b family data sheet, rev. 9.1 132 freescale semiconductor 11.2.7 pwm scale register 1 read: anytime write: anytime a write causes the scaler counter pwscnt1 to load t he pwscal1 value unless it is in special mode with discal = 1 in the pwtst register. pwm channels 2 and 3 can select clock s1 (scaled) as its input clock by setting the control bit pclk2 and pclk3 respectively. clock s1 is generated by dividing clock b by the value in the pwscal1 register plus one and dividing again by two. when pwscal1 = $ ff, clock b is divided by 256 then divided by two to generate clock s1. 11.2.8 pwm scale counter 1 value read: anytime pwscnt1 is a down-counter that, upon reaching $00, loads the value of pwscal1. address: $0046 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 11-10. pwm scale register 1 (pwscal1) address: $0047 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 11-11. pwm scale counter 1 value (pwscnt1)
pwm register descriptions m68hc12b family data sheet, rev. 9.1 freescale semiconductor 133 11.2.9 pwm channel counters 0?3 read: anytime write: anytime a write causes the pwm counter to reset to $00. in special mode, if discr = 1, a write does not reset the pwm counter. each counter may be read anytime without affecting the count or the operation of the corresponding pwm channel. writes to a counter cause the counter to be reset to $00 and force an immediate load of both duty and period registers with new values. to avoid a truncated pwm period, write to a counter while the counter is disabled. in left-aligned output mode, resetti ng the counter and starting the waveform output is controlled by a match between the period register a nd the value in the counter. in center-aligned output mode, the counters operate as up/down counters, where a match in period changes the counter direction. the duty register changes the state of the output during the period to determine the duty. when a channel is enabled, the associated pwm counte r starts at the count in the pwcntx register using the clock selected for that channel. in special mode, when discp = 1 and is configured for left-aligned output, a match of period does not reset the associated pwm counter. address: $0048 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 11-12. pwm channel counter 0 (pwcnt0) address: $0049 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 11-13. pwm channel counter 1 (pwcnt1) address: $004a bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 11-14. pwm channel counter 2 (pwcnt2) address: $004b bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 11-15. pwm channel counter 3 (pwcnt3)
pulse-width modulator (pwm) m68hc12b family data sheet, rev. 9.1 134 freescale semiconductor 11.2.10 pwm channel period registers 0?3 read: anytime write: anytime the value in the period register determines the period of the associated pwm channel. if written while the channel is enabled, the new value takes effect when the existing period terminates, forcing the counter to reset. the new period is then latched and is used until a new period value is written. reading this register returns the most recent value written. to start a new period immediately, wr ite the new period value and then write the counter, forcing a new period to start with the new period value. period = channel-clock-period (pwper + 1)(centr = 0) period = channel-clock-period pwper 2(centr = 1) address: $004c bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 11-16. pwm channel period register 0 (pwper0) address: $004d bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 11-17. pwm channel period register 1 (pwper1) address: $004e bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 11-18. pwm channel period register 2 (pwper2) address: $004f bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 11-19. pwm channel period register 3 (pwper3)
pwm register descriptions m68hc12b family data sheet, rev. 9.1 freescale semiconductor 135 11.2.11 pwm channel duty registers 0?3 read: anytime write: anytime the value in each duty register determines the duty of the associated pwm channel. when the duty value is equal to the counter value, the output changes stat e. if the register is written while the channel is enabled, the new value is held in a buffer until the counter rolls over or the channel is disabled. reading this register returns the most recent value written. if the duty register is greater than or equal to the val ue in the period register, there is no duty change in state. if the duty register is set to $ff, the output is always in the state which would normally be the state opposite the ppolx value. left-aligned output mode (centr = 0): duty cycle = [(pwdtyx + 1) / (pwperx + 1)] 100%(ppolx = 1) duty cycle = [(pwperx ? pwdtyx) / (pwperx + 1)] 100%(ppolx = 0) center-aligned output mode (centr = 1): duty cycle = [(pwperx ? pwdtyx) / pwperx] 100%(ppolx = 0) duty cycle = (pwdtyx / pwperx) 100%(ppolx = 1) address: $0050 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 11-20. pwm channel duty register 0 (pwdty0) address: $0051 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 11-21. pwm channel duty register 1 (pwdty1) address: $0052 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 11-22. pwm channel duty register 2 (pwdty2) address: $0053 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 11-23. pwm channel duty register 3 (pwdty3)
pulse-width modulator (pwm) m68hc12b family data sheet, rev. 9.1 136 freescale semiconductor 11.2.12 pwm control register read: anytime write: anytime pswai ? pwm halts while in wait mode bit 0 = continue pwm main clock generator while in wait mode. 1 = halt pwm main clock generator when the part is in wait mode. centr ? center-aligned output mode bit to avoid irregularities in the pwm output mode, write the centr bit only when pwm channels are disabled. 0 = pwm channels operate in left-aligned output mode. 1 = pwm channels operate in center-aligned output mode. rdpp ? reduced drive of port p bit 0 = full drive for all port p output pins 1 = reduced drive for all port p output pins pupp ? pullup port p enable bit 0 = disable port p pullups 1 = enable pullups for all port p input pins. psbck ? pwm stops while in background mode bit 0 = allows pwm to continue while in background mode 1 = disable pwm input clock while in background mode. address: $0054 bit 7654321bit 0 read: 0 0 0 pswai centr rdpp pupp psbck write: reset:00000000 = unimplemented figure 11-24. pwm control register (pwctl)
pwm register descriptions m68hc12b family data sheet, rev. 9.1 freescale semiconductor 137 11.2.13 pwm special mode register read: anytime write: only in special mode (smodn = 0) these bits are available only in special mode and are reset in normal mode. discr ? disable channel counter reset bit this bit disables the normal operation of resetti ng the channel counter when the channel counter is written. 0 = normal operation 1 = write to pwm channel counter does not reset channel counter. discp ? disable compare count period bit 0 = normal operation 1 = in left-aligned output mode, match of the period does not reset the associated pwm counter register. discal ? disable scale counter loading bit this bit disables the normal operation of loadi ng scale counters on a write to the associated scale register. 0 = normal operation 1 = write to pwscal0 and pwsca l1 does not load scale counters. 11.2.14 port p data register read: anytime write: anytime pwm functions share port p pins 3 to 0 and take precedence over the general-purpose port when enabled. when configured as input, a read returns the pin level. when configured as output, a read returns the latched output data. a write drives associated pins only if configur ed for output and the corresponding pwm channel is not enabled. after reset, all pins are general-purpose, high-impedance inputs. address: $0055 bit 7654321bit 0 read: discr discp discal 00000 write: reset:00000000 = unimplemented figure 11-25. pwm special mode register (pwtst) address: $0056 bit 7654321bit 0 read: pp7 pp6 pp5 pp4 pp3 pp2 pp1 pp0 write: pwm pwm3 pwm2 pwm1 pwm0 reset: unaffected by reset figure 11-26. port p data register (portp)
pulse-width modulator (pwm) m68hc12b family data sheet, rev. 9.1 138 freescale semiconductor 11.2.15 port p data direction register read: anytime write: anytime ddrp determines pin direction of port p when used for gene ral-purpose i/o. when cleared, i/o pin is configured for input. when set, i/o pin is configured for output. 11.3 pwm boundary cases the boundary conditions for the pwm channel duty registers and the pwm channel period registers cause the results shown in table 11-2 . 11.4 using the output compar e 7 feature to generate a pwm this timer exercise is intended to utilize the output compare function along with the output compare 7 new feature to generate a pwm waveform. it must allow for the duty used to drive a dc motor on the udlp1 board. the registers must be initialized accordingly tc7 = period and tc5 = high time (duty cycle). see figure 11-28 . note to verify program is working the dc motor must turn, the frequency, high time, and duty cycle must displayed on the lcd. figure 11-28. example waveform address: $0057 bit 7654321bit 0 read: ddp7 ddp6 ddp5 ddp4 ddp3 ddp2 ddp1 ddp0 write: reset:00000000 figure 11-27. port p data direction register (ddrp) table 11-2. pwm boundary conditions pwdtyx pwperx ppolx output $ff > $00 1 low $ff > $00 0 high pwperx ? 1 high pwperx ? 0 low ? $00 1 high ? $00 0 low high time high time = duty cycle period
using the output compare 7 feature to generate a pwm m68hc12b family data sheet, rev. 9.1 freescale semiconductor 139 11.4.1 pwm period calculation these parameters were used to calculate the high-time values shown in table 11-3 : period = $1000 (hex) = 4096 (decimal) e clock = 8 mhz prescaler = 4 frequency = (8 mhz) / (#clocks_count *prescaler) = (8 mhz) (4096*4) = 500 hz if period ($4096 clocks) => frequency = 500 hz 11.4.2 equipment for this exercise, use the m6 8hc912b32evb emulation board. table 11-3. pwm period calculations high-time values duty cycle hex count decimal count $0020 32 0% $0040 64 1.5% $0080 128 3.1% $0100 256 6.25% $0200 512 12.50% $0040 1024 25.00% $0080 2048 50.00% $0996 2454 60.00% $0c00 3072 75.00% $0d9a 3482 85.00% $1000 4096 100.00%
pulse-width modulator (pwm) m68hc12b family data sheet, rev. 9.1 140 freescale semiconductor 11.4.3 code listing note a comment line is deliminted by a se mi-colon. if there is no code before comment, an ?;? must be placed in the first column to avoid assembly errors. include 'equates.asm' ; equates for all registers ; ---------------------------------------------------------------------- ; main program ; ---------------------------------------------------------------------- org $7000 ; 16k on-board ram, user code data area, ; ; start main program at $7000 main: bsr timerinit ; subroutine used to initialize the timer: ; ; out. comp. chan. using oc7 & oc5, ; ; no interrupts ; ; oc7 = period & oc5 = high time of pwm done: bra done ; branch to itself, convinient for breakpoint ;* -------------------------------------------------------- ;* subroutine timerinit: initialize timer for pwm on oc5 ;* -------------------------------------------------------- timerinit: clr tmsk1 ; disable all interrupts movb #$0a,tmsk2 ; disable overflow interrupt, disable pull-up ; ; resistor function with normal drive capability ; ; and cntr reset by a succesful oc7 compare, ; ; prescaler = sys clock / 4. movb #$88,tctl1 ; init. oc5 to clear ouput line to zero on ; ; successful compare. movb #$a0,tios ; select channel 5 and 7 to act as output compare. movb #$20,oc7m ; initialize oc7 compare to affect oc5 pin(oc7m) movb #$20,oc7d ; enable oc7 to set output compare 5 pin high(oc7d). movw #$0800,tc7h ; load tc7 with "period" of the pwm movw #$0400,tc5h ; load tc5 with "high time" of the pwm. movb #$80,tscr ; enable timer, timer runs during wait state, ; ; and while in background mode, also clear flags ; ; normally. rts ; return from subroutine
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 141 chapter 12 standard timer (tim) 12.1 introduction the standard timer module (tim) for the mc68hc912b32 and mc68hc(9)12bc32 consists of a 16-bit software-programmable counter driven by a presca ler. it contains eight complete 16-bit input capture/output compare channels and one 16-bit pulse accumulator. see figure 12-2 . the mc68hc12be32 contains an enhanced capture ti mer (ect). the timer on the mc68hc12be32 is backward compatible with code used on the mc68hc912b32. see chapter 13 enhanced capture timer (ect) module for technical inform ation on this timer. this timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from less than a micros econd to many seconds. it can also generate pulse-width modulator (pwm) signals without cpu intervention. 12.2 timer registers input/output (i/o) pins default to general-purpose i/o lines until an internal function which uses that pin is specifically enabled. the ti mer overrides the state of the ddr to fo rce the i/o state of each associated port line when an output compare using a port line is enabled. in these cases, the data direction bits will have no effect on these lines. when a pin is assigned to output an on-chip peripheral f unction, writing to this porttn bit does not affect the pin, but the data is stored in an internal latch such that if the pin becomes available for general-purpose output the driven level will be th e last value written to the porttn bit. 12.2.1 timer input capture/ou tput compare se lect register read: anytime write: anytime ios7?ios0 ?input capture or output compare channel designator bits 0 = corresponding channel ac ts as an input capture. 1 = corresponding channel acts as an output compare. address: $0080 bit 7654321bit 0 read: ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 write: reset:00000000 figure 12-1. timer input capture/output compare select register (tios)
standard timer (tim) m68hc12b family data sheet, rev. 9.1 142 freescale semiconductor 12.3 block diagram figure 12-2. timer block diagram tff pad int oc7 pad int mux pamod pulse accumulator control registers 64 tc7 pin logic module clock 16-bit counter buffer latch tc7 input pin polarity ctl gate clock ctl timpt pin logic function, direction, and polarity ctl control registers prescaler divide ctl input capture/ output compare register 16-bit comparator intermodule bus oc output ic input buffer latch ? tioc tcre counter reset tcnt reset tcnt 16-bit counter prescaler pr2, pr1, pr0 timer count register module clock tctl1 and tctl2
block diagram m68hc12b family data sheet, rev. 9.1 freescale semiconductor 143 12.3.1 timer compare force register read: anytime, always returns $00 (1 state is transient) write: anytime foc7?foc0 ? force output compare action bits for channels 7?0 a write to this register with the corresponding dat a bit(s) set causes the ac tion which is programmed for output compare n to occur immediately. the action taken is the same as if a successful comparison had just taken place with the tcn register ex cept that the interrupt flag does not get set. 12.3.2 output comp are 7 mask register read: anytime write: anytime the bits of oc7m correspond bit-for-bit with the bi ts of the timer port (por tt). setting the oc7mn sets the corresponding port to be an output port regardless of the state of the ddrtn bit when the corresponding tiosn bit is set to be an output compare. this does not change the state of the ddrt bits. 12.3.3 output comp are 7 data register read: anytime write: anytime the bits of oc7d correspond bit-for-bit with the bits of the timer port (portt). when a successful oc7 compare occurs, for each bit that is set in oc7m, the corresponding data bit in oc7d is stored to the corresponding bit of the timer port. when the oc7mn bit is set, a successful oc7 action will override a successful oc6?oc0 compare action during the same cycle; therefore, the ocn acti on taken will depend on the corresponding oc7d bit. address: $0081 bit 7654321bit 0 read: foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 write: reset:00000000 figure 12-3. timer compare force register (cforc) address: $0082 bit 7654321bit 0 read: oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 write: reset:00000000 figure 12-4. output compare 7 mask register (oc7m) address: $0083 bit 7654321bit 0 read: oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 write: reset:00000000 figure 12-5. output compare 7 data register (oc7d)
standard timer (tim) m68hc12b family data sheet, rev. 9.1 144 freescale semiconductor 12.3.4 timer count register read: anytime write: has no meaning or effect in normal mode; only writable in special modes a full access for the counter register should take pl ace in one clock cycle. a separate read/write for high byte and low byte will give a different result than accessing them as a word. the period of the first count after a write to the tcnt registers may be a different size because the write is not synchronized with the prescaler clock. 12.3.5 timer system control register read: anytime write: anytime ten ? timer enable bit if for any reason the timer is not active, there is no 64 clock for the pulse accumulator since the e 64 is generated by the timer prescaler. 0 = disables timer, including the counter ; can be used for reducing power consumption 1 = allows timer to function normally tswai ? timer stops while in wait bit timer interrupts cannot be used to get the mcu out of wait. 0 = allows timer to continue running during wait 1 = disables timer when mcu is in wait mode address: $0084 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $0085 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 12-6. timer count register (tcnt) address: $0086 bit 7654321bit 0 read: ten tswai tsbck tffca 0000 write: reset:00000000 = unimplemented figure 12-7. timer system control register (tscr)
block diagram m68hc12b family data sheet, rev. 9.1 freescale semiconductor 145 tsbck ? timer stops while in background mode bit 0 = allows timer to continue running while in background mode 1 = disables timer when mcu is in background mode; useful for emulation tffca ? timer fast flag clear all bit 0 = allows timer flag cl earing to function normally 1 = for tflg1($8e), a read from an input capture or a write to the output compare channel ($90?$9f) causes the corresponding channel flag, cnf, to be cleared. for tflg2 ($8f), any access to the tcnt register ($84, $85) clears the tof flag. any access to the pacnt register ($a2 and $a3) clears the paovf and paif flags in the paflg register ($a1). this has the advantage of eliminating softw are overhead in a separate clear sequence. note extra care is required to avoid acci dental flag clearing due to unintended accesses. 12.3.6 timer control registers read: anytime write: anytime omn ? output mode oln ? output level these eight pairs of control bits are encoded to specif y the output action to be taken as a result of a successful ocn compare (see table 12-1 ). when either omn or oln is 1, the pin associated with ocn becomes an output tied to ocn regardless of the state of the associated ddrt bit. address: $0088 bit 7654321bit 0 read: om7ol7om6ol6om5ol5om4ol4 write: reset:00000000 figure 12-8. timer control register 1 (tctl1) address: $0089 bit 7654321bit 0 read: om3ol3om2ol2om1ol1om0ol0 write: reset:00000000 figure 12-9. timer control register 2 (tctl2) table 12-1. compare result output action omn oln action 0 0 timer disconnected from output pin logic 0 1 toggle ocn output line 1 0 clear ocn output line to 0 1 1 set ocn output line to 1
standard timer (tim) m68hc12b family data sheet, rev. 9.1 146 freescale semiconductor read: anytime write: anytime edgnb and edgna ? input capture edge control bits these 8 pairs of control bits configure th e input capture edge detector circuits. see table 12-2 . 12.3.7 timer interr upt mask registers read: anytime write: anytime the bits in tmsk1 correspond bit-for-bit with the bits in the tflg1 status register. if cleared, the corresponding flag is disabled from causing a hardware interrupt. if set, the corresponding flag is enabled to cause a hardware interrupt. address: $008a bit 7654321bit 0 read: edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a write: reset:00000000 figure 12-10. timer control register 3 (tctl3) address: $008b bit 7654321bit 0 read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a write: reset:00000000 figure 12-11. timer control register 4 (tctl4) table 12-2. edge detector circuit configuration edgnb edgna configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge (rising or falling) address: $008c bit 7654321bit 0 read: c7i c6i c5i c4i c3i c2i c1i c0i write: reset:00000000 figure 12-12. timer interrupt mask 1 register (tmsk1)
block diagram m68hc12b family data sheet, rev. 9.1 freescale semiconductor 147 c7i?c0i ? input capture/output compare x interrupt enable bits read: anytime write: anytime toi ? timer overflow interrupt enable bit 0 = interrupt inhibited 1 = hardware interrupt requested when tof flag set pupt ? timer pullup resistor enable bit this enable bit controls pullup resistors on the time r port pins when the pins are configured as inputs. 0 = disable pullup resistor function 1 = enable pullup resistor function rdpt ? timer drive reduction bit this bit reduces the effective output driver size which can reduce power supply current and generated noise depending upon pin loading. 0 = normal output drive capability 1 = enable output drive reduction function tcre ? timer counter reset enable bit this bit allows the timer counter to be re set by a successful output compare 7 event. 0 = counter reset inhibited and counter free runs 1 = counter reset by a successful output compare 7 if tc7 = $0000 and tcre = 1, tcnt stays at $0000 continuously. if tc7 = $ffff and tcre = 1, tof never gets set even though tcnt counts from $0000 through $ffff. pr2, pr1, and pr0 ? timer prescaler select bits these three bits specify the number of 2 stages that are to be inserted between the module clock and the timer counter. see table 12-3 . the newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal 0. address: $008d bit 7654321bit 0 read: toi 0 pupt rdpt tcre pr2 pr1 pr0 write: reset:00000000 = unimplemented figure 12-13. timer interrupt mask 2 register (tmsk2) table 12-3. prescaler selection pr2 pr1 pr0 prescale factor 000 1 001 2 010 4 011 8 100 16 101 32 110 reserved 111 reserved
standard timer (tim) m68hc12b family data sheet, rev. 9.1 148 freescale semiconductor 12.3.8 timer interr upt flag registers read: anytime write: used in the clearing mechanism; set bits cause corresponding bits to be cleared tflg1 indicates when interrupt conditions have occurred. to clear a bit in the flag register, write a 1 to the bit. writing a logic 0 does not affect current status of the bit. when tffca bit in tscr register is set, a read from an input capture or a write into an output compare channel ($90?$9f) causes the corresponding channel flag cnf to be cleared. c7f?c0f ? input capture/output compare channel n flag read: anytime write: used in the clearing mechanism; set bits cause corresponding bits to be cleared tflg2 indicates when interrupt conditions have occurred. to clear a bit in the flag register, set the bit to 1. any access to tcnt clears tflg2 register, if the tffca bit in tscr register is set. tof ? timer overflow flag set when 16-bit free-running timer overflows from $f fff to $0000. this bit is cleared automatically by a write to the tflg2 register with bit 7 set. for additional information, see the tcre control bit explanation found in 12.3.7 timer interrupt mask registers . address: $008e bit 7654321bit 0 read: c7f c6f c5f c4f c3f c2f c1f c0f write: reset:00000000 figure 12-14. timer interrupt flag 1 (tflg1) address: $008f bit 7654321bit 0 read: tof0000000 write: reset:00000000 figure 12-15. timer interrupt flag 2 (tflg2)
block diagram m68hc12b family data sheet, rev. 9.1 freescale semiconductor 149 12.3.9 timer input capture/ output compare registers address: $0090 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $0091 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 12-16. timer input capture/output compare register 0 (tc0) address: $0092 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $0093 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 12-17. timer input capture/output compare register 1 (tc1) address: $0094 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $0095 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 12-18. timer input capture/output compare register 2 (tc2)
standard timer (tim) m68hc12b family data sheet, rev. 9.1 150 freescale semiconductor address: $0096 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $0097 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 12-19. timer input capture/output compare register 3 (tc3) address: $0098 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $0099 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 12-20. timer input capture/output compare register 4 (tc4) address: $009a bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $009b bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 12-21. timer input capture/output compare register 5 (tc5)
block diagram m68hc12b family data sheet, rev. 9.1 freescale semiconductor 151 read: anytime write: anytime for output compare function; has no meaning or effect during input capture depending on the tios bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the correspond ing input capture edge detector or to trigger an output action for output compare. 12.3.10 pulse accumul ator control register read: anytime write: anytime address: $009c bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $009d bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 12-22. timer input capture/output compare register 6 (tc6) address: $009e bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $009f bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 12-23. timer input capture/output compare register 7 (tc7) address: $00a0 bit 7654321bit 0 read: 0 paen pamod pedge clk1 clk0 paovi pai write: reset:00000000 = unimplemented figure 12-24. pulse accumulator control register (pactl)
standard timer (tim) m68hc12b family data sheet, rev. 9.1 152 freescale semiconductor paen ? pulse accumulator system enable bit 0 = pulse accumulator system disabled 1 = pulse accumulator system enabled paen is independent from ten. pamod ? pulse accumulator mode bit 0 = event counter mode 1 = gated time accumulation mode pedge ? pulse accumulator edge control bit for pamod = 0 (event counter mode) 0 = falling edges on the pulse accumulator input pi n (pt7/pai) cause the count to be incremented. 1 = rising edges on the pulse accumulator input pin cause the count to be incremented. for pamod = 1 (gated time accumulation mode) 0 = pulse accumulator input pin high enables e 64 clock to pulse accumulator and the trailing falling edge on the pulse accumulator input pin sets the paif flag. 1 = pulse accumulator input pin low enables e 64 clock to pulse accumulator and the trailing rising edge on the pulse accumulator input pin sets the paif flag. if the timer is not active (ten = 0 in tscr), there is no 64 clock since the e 64 clock is generated by the timer prescaler. clk1 and clk0 ? clock select bits if the pulse accumulator is disabled (paen = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. the change from one selected clock to the other happens immediately after these bits are written. paovi ? pulse accumulator overflow interrupt enable bit 0 = interrupt inhibited 1 = interrupt requested if paovf is set pai ? pulse accumulator input interrupt enable bit 0 = interrupt inhibited 1 = interrupt requested if paif is set table 12-4. clock selection clk1 clk0 selected clock 0 0 use timer prescaler clock as timer counter clock 0 1 use paclk as input to timer counter clock 1 0 use paclk/256 as timer counter clock frequency 1 1 use paclk/65536 as timer counter clock frequency
block diagram m68hc12b family data sheet, rev. 9.1 freescale semiconductor 153 12.3.11 pulse accumulator flag register read: anytime write: anytime when the tffca bit in the tscr register is set, any acce ss to the pacnt register clears all the flags in the paflg register. paovf ? pulse accumulator overflow flag set when the 16-bit pulse accumulator overflows from $ffff to $0000. this bit is cleared automatically by a write to the paflg register with bit 1 set. paif ? pulse accumulator input edge flag set when the selected edge is detected at the pulse accumulator input pin. in event mode, the event edge triggers paif. in gated time accumulation mode, the trailing edge of the gate signal at the pulse accumulator input pin triggers paif. this bit is cleared automatically by a write to the paflg register with bit 0 set. 12.3.12 16-bit pulse a ccumulator count register read: anytime write: anytime full count register access should take place in one clock cycle. a separate read/write for high byte and low byte will give a different result than accessing them as a word. address: $00a1 bit 7654321bit 0 read: 000000paovfpaif write: reset:00000000 figure 12-25. pulse accumulator flag register (paflg) address: $00a2 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $00a3 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 12-26. 16-bit pulse accumulator count register (pacnt)
standard timer (tim) m68hc12b family data sheet, rev. 9.1 154 freescale semiconductor 12.3.13 timer test register read: anytime write: only in special mode (smodn = 0) tcbyp ? timer divider chain bypass bit 0 = normal operation 1 = 16-bit free-running timer counter is divided into two 8-bit halves and the prescaler is bypassed. the clock drives both halves directly. pcbyp ? pulse accumulator divider chain bypass bit 0 = normal operation 1 = 16-bit pulse accumulator counter is divided in to two 8-bit halves and the prescaler is bypassed. the clock drives both halves directly. 12.3.14 timer port data register read: anytime; inputs return pin level; outputs return pin driver input level write: data stored in an internal latch; drives pins only if configured for output note writes do not change pin state when the pin is configured for timer output. the minimum pulse width for pulse a ccumulator input should always be greater than two module clocks due to input synchronizer circuitry. the minimum pulse width for the input capture should always be greater than the width of two module clocks due to input synchronizer circuitry. address: $00ad bit 7654321bit 0 read:000000tcbyppcbyp write: reset:00000000 = unimplemented figure 12-27. timer test register (timtst) address: $00ae bit 7654321bit 0 read: pt7 pt6 pt5 pt4 pt3 pt2 pt1 pt0 write: reset:00000000 timer: i/oc7 i/oc6 i/oc5 i/oc4 i/oc3 i/oc2 i/oc1 i/oc0 pa: pai figure 12-28. timer port data register (portt)
timer operation in modes m68hc12b family data sheet, rev. 9.1 freescale semiconductor 155 12.3.15 data direction register for timer port read: anytime write: anytime 0 = configures the corresponding i/o pin for input only 1 = configures the corresponding i/o pin for output the timer forces the i/o state to be an output for each timer port pin associated with an enabled output compare. in these cases the data direction bits will not be changed, but they have no affect on the direction of these pins. the ddrt will revert to controlling the i/o dire ction of a pin when the associated timer output compare is disabled. input c aptures do not override the ddrt settings. 12.4 timer operation in modes stop ? timer is off since both pclk and eclk are stopped. bdm? timer keeps running, unless tsbck = 1. wait ? counters keep running, unless tswai = 1. normal ? timer keeps running, unless ten = 0. ten = 0 ?all timer operations are stopped, registers may be accessed. gated pulse accumulator 64 clock is also disabled. paen = 0 ?all pulse accumula tor operations are stopped. registers may be accessed. address: $00af bit 7654321bit 0 read: ddt7 ddt6 ddt5 ddt4 ddt3 ddt2 ddt1 ddt0 write: reset:00000000 figure 12-29. data direction register for timer port (ddrt)
standard timer (tim) m68hc12b family data sheet, rev. 9.1 156 freescale semiconductor 12.5 using the output compare fu nction to generate a square wave this timer exercise is intended to utilize the out put compare function to generate a square wave of predetermined duty cycle and frequency. square wave frequency 1000 hz, duty cycle 50% the program generates a square wave, 50 percent duty cycle, on output compare 2 (oc2). the signal will be measured by the hc11 on the udlp1 board. it assumes a 8.0 mhz operating frequency for the e clock. the control registers are initialized to disa ble interrupts, configure for proper pin control action and also the tc2h register for desired compare va lue. the appropiate count must be calculated to achieve the desired frequency and duty cycle. for ex ample: for a 50 percent duty, 1 khz signal each period must consist of 2048 counts or 1024 counts high and 1024 counts low. in essence a $0400 is added to generate a frequency of 1 khz. 12.5.1 sample calculatio n to obtain period counts the sample calculation to obtain period counts is: for 1000 hz frequency: ? e-clock = 8 mhz ? ic/oc resolution factor = 1/(e-clock/prescaler) ? if the prescaler = 4, then output compare resolution is 0.5 s for a 1 khz, 50 percent duty cycle: ? 1/f = t = 1/1000 = 1 ms ? f for output compare = prescaler/e clock = 2 mhz figure 12-30. example waveform 12.5.2 equipment for this exercise, use the m6 8hc912b32evb emulation board. 12.5.3 code listing note a comment line is deliminted by a se mi-colon. if there is no code before comment, an ?;? must be placed in the first column to avoid assembly errors. 0.5 ms number of clocks = f * d 1 ms therefore, #clocks = (2 mhz) * (0.5 ms) = 1024 = $0400
using the output compare functi on to generate a square wave m68hc12b family data sheet, rev. 9.1 freescale semiconductor 157 ---------------------------------------------------------------------- ; main program ; ---------------------------------------------------------------------- org $7000 ; 16k on-board ram, user code data area, ; ; start main program at $7000 main: bsr timerinit ; subroutine used to initialize the timer: ; ; output compare channel, no interrupts bsr sqwave ; subroutine to generate square wave done: bra done ; branch to itself, convinient for breakpoint ;* ----------------------------------------------------------------- ;* subroutine timerinit: initialize timer for output compare on oc2 ;* ----------------------------------------------------------------- timerinit: clr tmsk1 ; disable all interrupts movb #$02,tmsk2 ; disable overflow interrupt, disable pull-up ; ; resistor function with normal drive capability ;; and free running counter, prescaler = sys clock/4. movb #$10,tctl2 ; initialize oc2 to toggle on successful compare. movb #$04,tios ; select channel 2 to act as output compare. movw #$0400,tc2h ; load tc2 reg with initial compare value. movb #$80,tscr ; enable timer, timer runs during wait state, and ; ; while in background mode, also clear flags ; ; normally. rts ; return from subroutine ;* ------------------------------ ;* subroutine: sqwave ;* ------------------------------ sqwave: ;* ------- clearflg: ;* ------- ;* to clear the c2f flag: 1) read tflg1 when ;* c2f is set and then 2) write a logic "one" to c2f. ldaa tflg1 ; to clear oc2 flag, first it must be read, oraa #$04 ; then a "1" must be written to it staa tflg1 wtflg: brclr tflg1,#$04,wtflg ; wait (polling) for c2f flag ldd tc2h ; loads value of compare from tc2 reg. addd #$0400 ; add hex value of 500us high time std tc2h ; set-up next transition time in 500 us bra clearflg ; continuously add 500 us, branch to clearflag rts ; return from subroutine end ; end of program
standard timer (tim) m68hc12b family data sheet, rev. 9.1 158 freescale semiconductor
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 159 chapter 13 enhanced capture timer (ect) module 13.1 introduction the m68hc12 enhanced capture timer (ect) module has the features of the m68hc12 standard timer (tim) module enhanced by additional features in order to enlarge the field of applications. these additional features are: 16-bit buffer register for four input capture (ic) channels four 8-bit pulse accumulators: ? 8-bit buffer registers associated with the four buffered ic channels ? configurable as two 16-bit pulse accumulators 16-bit modulus down-counter with 4-bit prescaler four user selectable delay counters for input noise immunity increase main timer prescaler extended to 7-bit this section describes the standard timer found on the mc68hc912b32 as well as the additional features found on the mc68hc12be32. 13.2 basic timer overview the basic timer consists of a 16-bit, software-programm able counter driven by a prescaler. this timer can be used for many purposes, including input wavefo rm measurements while simultaneously generating an output waveform. pulse widths can vary from microseconds to many seconds. a full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. accessing high byte and low byte sepa rately for all of these registers may not yield the same result as accessing them in one word. 13.3 enhanced capture timer modes of operation the enhanced capture timer has eight input capture, output compare (ic/oc) channels same as on the m68hc12 standard timer (timer channels tc0?tc7). whe n channels are selected as input capture by selecting the iosx bit in the timer input capture/output compare select register (tios), they are called input capture (ic) channels. four ic channels are the same as on the standard timer with one capture register which memorizes the timer value captured by an action on the associated input pin. four other ic channels, in addition to the capture register, also have one buffer called holding regi ster. this permits the register to memorize two different timer values without generation of any interrupt. four 8-bit pulse accumulators are associated with the four buffered ic channels. each pulse accumulator has a holding register to memorize their value by an action on its external input. each pair of pulse accumulators can be used as a 16-bit pulse accumulator.
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 160 freescale semiconductor the 16-bit modulus down-counter can control the transfe r of the ic register?s contents and the pulse accumulators to the respective holding registers for a given period, every time the count reaches 0. the modulus down-counter can also be used as a stand-alone timebase with periodic interrupt capability. 13.3.1 ic channels the ic channels are composed of four sta ndard ic registers and four buffered ic channels. an ic register is empty when it has been read or latched into the holding register. a holding register is empty when it has been read. 13.3.1.1 non-buffered ic channels the main timer value is memorized in the ic register by a valid input pin transition. if the corresponding novwx bit of the input control overwrite register (icovw) is cleared, with a new occurrence of a capture, the contents of ic register are overwritten by the new value. if the corresponding novwx bit of the icovw regist er is set, the capture register cannot be written unless it is empty. this will prevent the captured value to be overwritten until it is read. 13.3.1.2 buffered ic channels there are two modes of operations for the buffered ic channels. ic latch mode (see figure 13-1 ): when enabled (latq = 1), the main timer value is memorized in the ic register by a valid input pin transition. the value of the buffered ic register is la tched to its holding register by the modulus counter for a given period when the count reaches 0, by a wr ite $0000 to the modulus counter or by a write to iclat in the 16-bit modulus down-counter control register (mcctl). if the corresponding novwx bit of the icovw register is cleared, with a new occurrence of a capture, the contents of ic register are overwri tten by the new value. in case of latching, the contents of its holding register are overwritten. if the corresponding novwx bit of the icovw register is set, the capture register or its holding register cannot be written by an event unless they are empty (see 13.3.1 ic channels ). this will prevent the captured value to be overwritten until it is read or latched in the holding register. ic queue mode (see figure 13-2 ): when enabled (latq = 0), the main timer value is memorized in the ic register by a valid input pin transition. if the corresponding novwx bit of the icovw register is cleared, with a new occurrence of a capture, the value of the ic register will be transferred to its holding register and the ic register memorizes the new timer value. if the corresponding novwx bit of the icovw register is set, the capture register or its holding register cannot be written by an event unless they are empty (see 13.3.1 ic channels ). in queue mode, reads of the holding register will latch the corresponding pulse accumulator value to its holding register.
enhanced capture time r modes of operation m68hc12b family data sheet, rev. 9.1 freescale semiconductor 161 figure 13-1. timer block diagram in latch mode 16 bit main timer pt1 comparator tc0h hold pt0 pt3 pt2 pt4 pt5 pt6 pt7 edg0 edg1 edg2 edg3 mux prescaler m clock 16-bit load register 16-bit modulus 0 reset edg0 edg1 edg2 edg4 edg5 edg3 edg6 edg7 1, 2, ..., 128 1, 4, 8, 16 16-bit free-running latch underflow main timer prescaler tc0 capture/compare pin delay p clock tc1h hold tc2h hold tc3h hold mux mux mux pa0h hold pac0 0 reset pa1h hold pac1 0 reset pa2h hold pac2 0 reset pa3h hold pac3 write $0000 to modulus iclat, latq, bufen (force latch) latq (mdc latch down counter logic pin logic pin logic pin logic pin logic pin logic pin logic pin logic counter delay counter delay counter delay counter register comparator tc1 capture/compare register register register register register register register register register comparator tc2 capture/compare register comparator tc3 capture/compare register comparator tc4 capture/compare register comparator tc5 capture/compare register comparator tc6 capture/compare register comparator tc7 capture/compare register counter enable)
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 162 freescale semiconductor figure 13-2. timer block diagram in queue mode 16 bit main timer pt1 comparator tc0h hold pt0 pt3 pt2 pt4 pt5 pt6 pt7 edg0 edg1 edg2 edg3 mux prescaler m clock 16-bit load register 16-bit modulus 0 reset edg0 edg1 edg2 edg4 edg5 edg3 edg6 edg7 1, 2, ..., 128 1, 4, 8, 16 16-bit free-running latch0 main timer prescaler tc0 capture/compare pin delay p clock mux mux mux pa0h hold pac0 0 reset pac1 0 reset pac2 0 reset pac3 latch1 latch3 latch2 down counter logic pin logic pin logic pin logic pin logic pin logic pin logic pin logic counter delay counter delay counter delay counter register comparator tc1 capture/compare register comparator tc2 capture/compare register comparator tc3 capture/compare register comparator tc4 capture/compare register comparator tc5 capture/compare register comparator tc6 capture/compare register comparator tc7 capture/compare register register tc1h hold register tc2h hold register tc3h hold register register pa3h hold register pa2h hold register pa1h hold register latq , bufen (queue mode) read tc3h hold register read tc2h hold register read tc1h hold register read tc0h hold register
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 163 13.3.2 pulse accumulators four 8-bit pulse accumulators with four 8-bit holding registers are associated with the four ic buffered channels. see figure 13-3 . a pulse accumulator counts the number of active edges at the input of its channel. the user can prevent 8-bit pulse accumulators from counting further than $ff by pacmx control bit in input control system control register (icsys). in this case, a value of $ff means that 255 counts or more have occurred. each pair of pulse accumulators can be used as a 16-bit pulse accumulator. see figure 13-4 . for more information on the two modes of operation for the pulse accumulators, see 13.3.2.1 pulse accumulator latch mode and 13.3.2.2 pulse accumulator queue mode . 13.3.2.1 pulse accumulator latch mode the value of the pulse accumulator is transferred to its holding register when the modulus down-counter reaches zero, a write $0000 to the modulus counter, or when the force latch control bit iclat is written. at the same time, the pulse accumulator is cleared. 13.3.2.2 pulse accumulator queue mode when queue mode is enabled, reads of an input capture hol ding register will transfer the contents of the associated pulse accumulator to its holding register. at the same time, the pulse accumulator is cleared. 13.3.3 modulus down-counter the modulus down-counter can be used as a timebase to generate a periodic interrupt. it can also be used to latch the values of the ic registers and th e pulse accumulators to their holding registers. the action of latching can be program med to be periodic or only once. 13.4 timer registers input/output pins default to general-purpose input/output (i/o) lines until an intern al function which uses that pin is specifically enabled. the timer overrides the state of the ddr to force the i/o state of each associated port line when an output compare using a port line is enabled. in these cases, the data direction bits will have no effect on these lines. when a pin is assigned to output an on-chip peripheral function, writing to this portt bit does not affect the pin. the data is stored in an internal latch such that if the pin becomes available for general-purpose output, the driven level will be the la st value written to the portt bit.
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 164 freescale semiconductor figure 13-3. 8-bit pulse accumulators block diagram host cpu data bus pt0 load holding register and reset pulse accumulator 0 0 edg3 edg2 edg1 edg0 edge detector delay counter interrupt interrupt pt1 edge detector delay counter pt2 edge detector delay counter pt3 edge detector delay counter 8-bit pac0 (pacn0) pa0h holding 0 8-bit pac1 (pacn1) pa1h holding 0 8-bit pac2 (pacn2) pa2h holding 0 8-bit pac3 (pacn3) pa3h holding register register register register
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 165 figure 13-4. 16-bit pulse accumulators block diagram edge detector 8-bit pac2 intermodule bus 8-bit pac3 pt7 pt0 m clock divide by 64 clock select clk0 clk1 4:1 mux timclk paclk paclk / 256 paclk / 65536 prescaled clock from timer (timer clock) interrupt mux (pamod) edge detector paca delay counter 8-bit pac0 8-bit pac1 interrupt pacb (pacn3) (pacn2) (pacn1) (pacn0)
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 166 freescale semiconductor 13.4.1 timer input capture/ou tput compare se lect register read: anytime write: anytime ios[7:0] ? input capture or output compare channel configuration bits 0 = the corresponding channel ac ts as an input capture. 1 = the corresponding channel ac ts as an output compare. 13.4.2 timer compare force register read: anytime but, will always retu rn $00 (1 state is transient). write: anytime foc[7:0] ? force output compare action bits for channel 7?0 a write to this register with the corresponding dat a bit(s) set causes the ac tion which is programmed for output compare ?n? to occur immediately. the action taken is the same as if a successful comparison had just taken place with the tcn register except the interrupt flag does not get set. 13.4.3 output comp are 7 mask register read: anytime write: anytime address: $0080 bit 7654321bit 0 read: ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 write: reset:00000000 figure 13-5. timer input capture/output compare select register (tios) address: $0081 bit 7654321bit 0 read: foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 write: reset:00000000 figure 13-6. timer compare force register (cforc) address: $0082 bit 7654321bit 0 read: oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 write: reset:00000000 figure 13-7. output compare 7 mask register (oc7m)
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 167 oc7m[7:0] bits the bits of oc7m correspond bit-for-bit with the timer port (portt) bits. se tting the oc7mn will set the corresponding port to be an output port regardless of the state of the ddrtn bit, when the corresponding tiosn bit is set to be an output com pare. this does not change the state of the ddrt bits. at successful oc7, for each bit that is set in oc7m, the corresponding data bit oc7d is stored to the corresponding bit of the timer port. see figure 13-8 . figure 13-8. block diagram for port 7 with output compare/pulse accumulator a note oc7m has priority over output action on the timer port enabled by omn and oln bits in tctl1 and tctl2. if an oc7m bit is set, it prevents the action of corresponding om and ol bits on the selected timer port. 13.4.4 output comp are 7 data register read: anytime write: anytime oc7d[7:0] bits the bits of oc7d correspond bit-for-bit with the bits of the timer port (portt). when a successful oc7 compare occurs, for each bit that is set in oc7m, the corresponding data bit in oc7d is stored to the corresponding bit of the timer port. when the oc7mn bit is set, a successful oc7 action will override a successf ul oc[6:0] compare action during the same cycle; therefore, the ocn acti on taken will depend on the corresponding oc7d bit. address: $0083 bit 7654321bit 0 read: oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 write: reset:00000000 figure 13-9. output compare 7 data register (oc7d) pulse accumulator a pad om7 = 1 or ol7 = 1 or oc7m7 = 1 oc7
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 168 freescale semiconductor 13.4.5 timer count registers read: anytime write: has no meaning or effect in the normal mode; only writable in special modes (smodn = 0) the 16-bit main timer is an up-counter. a full access for the counter register should take pl ace in one clock cycle. a separate read/write for high byte and low byte will give a different result than accessing them as a word. the period of the first count after a write to the tcnt registers may be a different size because the write is not synchronized with the prescaler clock. 13.4.6 timer system control register read: anytime write: anytime ten ? timer enable bit if for any reason the timer is not active, there is no 64 clock for the pulse accumulator since the e 64 is generated by the timer prescaler. 0 = disables the main timer, including the count er; can be used for reducing power consumption 1 = allows the timer to function normally address: $0084 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $0085 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 13-10. timer count registers (tcnt) address: $0086 bit 7654321bit 0 read: ten tswai tsbck tffca write: reset:00000000 = unimplemented figure 13-11. timer system control register (tscr)
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 169 tswai ? timer module stops while in wait bit tswai also affects pulse accumulators and modulus down counters. 0 = allows the timer module to continue running during wait 1 = disables the timer module when the mcu is in wait mode. timer interrupts cannot be used to get the mcu out of wait. tsbck ? timer and modulus counter stop while in background mode bit tbsck does not stop the pulse accumulator. 0 = allows the timer and modul us counter to continue running while in background mode 1 = disables the timer and modul us counter whenever the mcu is in background mode. this is useful for emulation. tffca ? timer fast flag clear all bit 0 = allows the timer flag clearing to function normally 1 = for tflg1($8e), a read from an input capture or a write to the output compare channel ($90?$9f) causes the corresponding channel flag, cnf, to be cleared. for tflg2 ($8f), any access to the tcnt register ($84, $85) clears the tof flag. any access to the pacn3 and pacn2 registers ($a2, $a3) clears the paovf and paif flags in the paflg register ($a1). any access to the pacn1 and pacn0 registers ($a4, $a5) clears the pbovf flag in the pbflg register ($b1). this has the advantage of eliminating software overhead in a separate clear sequence. extra care is required to avoid accidental flag clearing due to unintended accesses. 13.4.7 timer control registers read: anytime write: anytime omn bits ? output mode oln bits ? output level these eight pairs of control bits are encoded to specif y the output action to be taken as a result of a successful ocn compare (see table 13-1 ). when either omn or oln is 1, the pin associated with ocn becomes an output tied to ocn regardless of the state of the associated ddrt bit. note to enable output action by omn and oln bits on the timer port, the corresponding bit in oc7m should be cleared. address: $0088 bit 7654321bit 0 read: om7ol7om6ol6om5ol5om4ol4 write: reset:00000000 figure 13-12. timer control register 1 (tctl1) address: $0089 bit 7654321bit 0 read: om3ol3om2ol2om1ol1om0ol0 write: reset:00000000 figure 13-13. timer control register 2 (tctl2)
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 170 freescale semiconductor to operate the 16-bit pulse accumulators a and b (paca and pacb) independently of input capture or output compare 7 and 0, respectively, the user mu st set the corresponding bits iosn = 1, omn = 0, and oln = 0. oc7m7 or oc7m0 in the oc7m register must also be cleared. read: anytime write: anytime edgnb and edgna ? input capture edge control bits these eight pairs of control bits configure the input capture edge detector circuits. see table 13-2 . table 13-1. compare result output action omn oln action 0 0 timer disconnected from output pin logic 0 1 toggle ocn output line 1 0 clear ocn output line to 0 1 1 set ocn output line to 1 address: $008a bit 7654321bit 0 read: edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a write: reset:00000000 figure 13-14. timer control register 3 (tctl3) address: $008b bit 7654321bit 0 read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a write: reset:00000000 figure 13-15. timer control register 4 (tctl4) table 13-2. edge detector circuit configuration edgnb edgna configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge (rising or falling)
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 171 13.4.8 timer interr upt mask registers read: anytime write: anytime c7i?c0i ? input capture/output compare x interrupt enable bits the bits in tmsk1 correspond bit-for-bit with the bits in the tflg1 status register. if cleared, the corresponding flag is disabl ed from causing a hardware interrupt. if set, the corresponding flag is enabled to cause a hardware interrupt. read: anytime write: anytime toi ? timer overflow interrupt enable bit 0 = interrupt inhibited 1 = hardware interrupt requested when tof flag set pupt ? timer port pullup resistor enable bit this enable bit controls pullup resistors on the time r port pins when the pins are configured as inputs. 0 = disable pullup resistor function 1 = enable pullup resistor function rdpt ? timer port drive reduction bit this bit reduces the effective output driver size which can reduce power supply current and generated noise depending upon pin loading. 0 = normal output drive capability 1 = enable output drive reduction function tcre ? timer counter reset enable bit this bit allows the timer counter to be reset by a successful output compare 7 event. this mode of operation is similar to an up-counting modulus counter. 0 = counter reset inhibited and counter runs free 1 = counter reset by a successful output compare 7 note if tc7 = $0000 and tcre = 1, tcnt will stay at $0000 continuously. if tc7 = $ffff and tcre = 1, tof will never be set when tcnt is reset from $ffff to $0000. address: $008c bit 7654321bit 0 read: c7i c6i c5i c4i c3i c2i c1i c0i write: reset:00000000 figure 13-16. timer interrupt mask 1 register (tmsk1) address: $008d bit 7654321bit 0 read: toi 0 pupt rdpt tcre pr2 pr1 pr0 write: reset:00000000 figure 13-17. timer interrupt mask 2 register (tmsk2)
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 172 freescale semiconductor pr2, pr1, and pr0 ? timer prescaler select bits these three bits specify the number of 2 stages that are to be inserted between the module clock and the main timer counter. see table 13-3 . the newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal 0. 13.4.9 main timer in terrupt flag registers read: anytime write: used in the clearing mechanism (s et bits cause corresponding bits to be cleared). writing a 0 will not affect current bit status. c7f?c0f ? input capture/output compare channel n flag tflg1 indicates when interrupt conditions have occurred. to clear a bit in the flag register, write a 1 to the bit. use of the tfmod bit in the input control system cont rol register (icsys) register ($ab) in conjunction with the use of the icovw register ($aa) allows a timer interrupt to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture. when tffca bit in tscr register is set, a read from an input capture or a write into an output compare channel ($90?$9f) will cause the correspondi ng channel flag cnf to be cleared. see figure 13-19 . table 13-3. prescaler selection value pr2 pr1 pr0 prescale factor 0000 1 1001 2 2010 4 3011 8 4100 16 5101 32 6110 64 7111 128 address: $008e bit 7654321bit 0 read: c7f c6f c5f c4f c3f c2f c1f c0f write: reset:00000000 figure 13-18. main timer interrupt flag 1 (tflg1)
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 173 figure 13-19. c3f?c0f interrupt flag setting read: anytime write: used in clearing mechanism (set bits cause corresponding bits to be cleared). any access to tcnt will clear the tflg2 register, if the tffca bit in the tscr register is set. tflg2 indicates when interrupt conditions have occurred. to clear a bit in the flag register, set the bit to 1. tof ? timer overflow flag tof is set when the 16-bit free-running timer over flows from $ffff to $0000. this bit is cleared automatically by a write to the tflg2 register with bit 7 set. see the explanation of the tcre control bit in 13.4.8 timer interrupt mask registers .) 13.4.10 timer input captur e/output compare registers address: $008f bit 7654321bit 0 read: tof0000000 write: reset:00000000 figure 13-20. main timer interrupt flag 2 (tflg2) address: $0090?$0091 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-21. timer input capture/output compare register 0 (tc0) ptn edge delay 16-bit main timer tcnh ic holding bufen ? latq ? tfmod set cnf detector counter register tcn input capture register interrupt
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 174 freescale semiconductor address: $0092?$0093 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-22. timer input capture/output compare register 1 (tc1) address: $0094?$0095 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-23. timer input capture/output compare register 2 (tc2) address: $0096?$0097 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-24. timer input capture/output compare register 3 (tc3) address: $0098?$0099 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-25. timer input capture/output compare register 4 (tc4)
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 175 read: anytime write: anytime for output compare function depending on the tios bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the correspond ing input capture edge detector or to trigger an output action for output compare. writes to these registers have no meaning or effect during input capture. all timer input capture/output compare registers are reset to $0000. address: $009a?$009b bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-26. timer input capture/output compare register 5 (tc5) address: $009c?$009d bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-27. timer input capture/output compare register 6 (tc6) address: $009e?$009f bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-28. timer input capture/output compare register 7 (tc7)
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 176 freescale semiconductor 13.4.11 16-bit pulse accum ulator a control register read: anytime write: anytime sixteen-bit pulse accumulator a (paca) is formed by cascading the 8-bit pulse accumulators pac3 and pac2. when paen is set, the paca is enabled . the paca shares the input pin with ic7. paen ? pulse accumulator a system enable bit paen is independent from ten. with timer disabled, the pulse accumu lator can still function unless the pulse accumulator is disabled. 0 = 16-bit pulse accumulator a system disa bled. eight-bit pac3 and pac2 can be enabled when their related enable bits in icpacr ($a8) are set. pulse accumulator input edge flag (paif) function is disabled. 1 = pulse accumulator a system enabled. the two 8-bit pulse accumulators, pac3 and pac2, are cascaded to form the paca 16-bit pulse accumulator. when paca in enabled, the pacn3 and pacn2 registers? contents are, respectively, the high and low byte of the paca. pa3en and pa2en control bits in icpacr ($a8) have no e ffect. pulse accumulator input edge flag (paif) function is enabled. pamod ? pulse accumulator mode bit 0 = event counter mode 1 = gated time accumulation mode pedge ? pulse accumulator edge control bit for pamod bit = 0, event counter mode 0 = falling edges on pt7 pin cause the count to be incremented. 1 = rising edges on pt7 pin cause the count to be incremented. for pamod bit = 1, gated time accumulation mode 0 = pt7 input pin high enables m divided by 64 cloc k to pulse accumulator and the trailing falling edge on pt7 sets the paif flag. 1 = pt7 input pin low enables m divided by 64 cloc k to pulse accumulator and the trailing rising edge on pt7 sets the paif flag. note if the timer is not active (ten = 0 in tscr), there is no divide-by-64 since the e 64 clock is generated by the timer prescaler. address: $00a0 bit 7654321bit 0 read: 0 paen pamod pedge clk1 clk0 paovi pai write: reset:00000000 = unimplemented figure 13-29. 16-bit pulse accumulator a control register (pactl) pamod pedge pin action 0 0 falling edge 0 1 rising edge 1 0 divide by 64 clock enabled with pin high level 1 1 divide by 64 clock enabled with pin low level
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 177 clk1 and clk0 ? clock select bits if the pulse accumulator is disabled (paen = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. the change from one selected clock to the other happens immediately after these bits are written. paovi ? pulse accumulator a overflow interrupt enable bit 0 = interrupt inhibited 1 = interrupt requested if paovf is set pai ? pulse accumulator input interrupt enable bit 0 = interrupt inhibited 1 = interrupt requested if paif is set 13.4.12 pulse accumul ator a flag register read: anytime write: anytime when the tffca bit in the tscr register is set, any acce ss to the pacnt register will clear all the flags in the paflg register. paovf ? pulse accumulator a overflow flag set when the 16-bit pulse accumulator a overflows from $ffff to $0000 or when 8-bit pulse accumulator 3 (pac3) overflows from $ff to $00. this bit is cleared automatically by a write to the paflg register with bit 1 set. paif ? pulse accumulator input edge flag set when the selected edge is detected at the pt7 input pin. in event mode, the event edge triggers paif and, in gated time accumulation mode, the trailing edge of the gate signal at the pt7 input pin triggers paif. this bit is cleared by a write to the paflg register with bit 0 set. any access to the pacn3 and pacn2 registers will clear all the flags in this register when tffca bit in register tscr ($86) is set. clk1 clk0 clock source 0 0 use timer prescaler clock as timer counter clock 0 1 use paclk as input to timer counter clock 1 0 use paclk/256 as timer counter clock frequency 1 1 use paclk/65,536 as timer counter clock frequency address: $00a1 bit 7654321bit 0 read: 000000paovfpaif write: reset:00000000 figure 13-30. pulse accumulator a flag register (paflg)
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 178 freescale semiconductor 13.4.13 pulse accumul ators count registers read: anytime write: anytime the two 8-bit pulse accumulators, pac3 and pac2, are cascaded to form the paca 16-bit pulse accumulator. when paca in enabled (paen = 1 in pactl, $a0) the pacn3 and pacn2 registers? contents are, respectively, the high and low bytes of the paca. when pacn3 overflows from $ff to $00, the interrupt flag paovf in paflg ($a1) is set. full count register access should take place in one clock cycle. a separate read/write for high byte and low byte will give a different result than accessing them as a word. read: anytime write: anytime address: $00a2 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-31. pulse accumulator count register 3 (pacn3) address: $00a3 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-32. pulse accumulator count register 2 (pacn2) address: $00a4 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-33. pulse accumulator count register 1 (pacn1) address: $00a5 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-34. pulse accumulator count register 0 (pacn0)
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 179 the two 8-bit pulse accumulators, pac1 and pac0, are cascaded to form the pacb 16-bit pulse accumulator. when pacb in enabled, (pben = 1 in pbctl, $b0) the pacn1 and pacn0 register contents are, respectively, the high and low bytes of the pacb. when pacn1 overflows from $ff to $00, the interrupt flag pbovf in pbflg ($b1) is set. full count register access should take place in one clock cycle. a separate read/write for high byte and low byte will give a different result than accessing them as a word. 13.4.14 16-bit modulus do wn-counter control register read: anytime write: anytime mczi ? modulus counter underflow interrupt enable bit 0 = modulus counter interrupt is disabled. 1 = modulus counter interrupt is enabled. modmc ? modulus mode enable bit 0 = the counter counts once from the value written to it and will stop at $0000. 1 = modulus mode is enabled. when the counter reaches $0000, the counter is loaded with the latest value written to the modulus count register. note for proper operation, the mcen bit should be cleared before modifying the modmc bit to reset the modulus counter to $ff. rdmcl ? read modulus down-counter load bit 0 = reads of the modulus count register will re turn the present value of the count register. 1 = reads of the modulus count register will return the contents of the load register. iclat ? input capture force latch action bit when input capture latch mode is enabled (latq and bu fen bit in icsys ($ab) are set), writing 1 to this bit immediately forces the contents of the input capture registers tc0 to tc3 and their corresponding 8-bit pulse accumulators to be latched in to the associated holding registers. the pulse accumulators will be automatically cl eared when the latch action occurs. writing 0 to this bit has no effect. read of this bit aways will return 0. flmc ? force load register into the modulus counter count register bit this bit is active only when the modulus down-count er is enabled (mcen = 1). writing a 1 into this bit loads the load register into the modulus counter count register. this also resets the modulus counter prescaler. writing 0 to this bit has no effect. when modmc = 0, the counter starts counting and st ops at $0000. reads of this bit will return always 0. address: $00a6 bit 7654321bit 0 read: mczi modmc rdmcl iclat flmc mcen mcpr1 mcpr0 write: reset:00000000 figure 13-35. 16-bit modulus down-counter control register (mcctl)
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 180 freescale semiconductor mcen ? modulus down-counter enable bit when mcen = 0, the counter is preset to $ffff. this will prevent an early interrupt flag when the modulus down-counter is enabled. 0 = modulus counter disabled. 1 = modulus counter is enabled. mcpr1 and mcpr0 ? modulus counter prescaler select bits these two bits specify the division rate of the modulus counter prescaler. the newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. 13.4.15 16-bit modulus down-counter flag register read: anytime write: only for clearing bit 7 mczf ? modulus counter underflow interrupt flag the flag is set when the modulus down-counter reaches $0000. writing 1 to this bit clears the flag. writing 0 has no effect. any access to the mccnt regi ster will clear the mczf flag in this register when tffca bit in register tscr ($86) is set. polf3?polf0 ? first input capture polarity status bits this are read-only bits. writing to t hese bits has no effect. each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch has been read. each polfx corresponds to a timer portx input. 0 = the first input capture has been caused by a falling edge. 1 = the first input capture has been caused by a rising edge. mcpr1 mcpr0 prescalar division rate 00 1 01 4 10 8 11 16 address: $00a7 bit 7654321bit 0 read: mczf 0 0 0 polf3 polf2 polf1 polf0 write: reset:00000000 figure 13-36. 16-bit modulus down-counter flag register (mcflg)
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 181 13.4.16 input control pulse accumulators control register read: anytime write: anytime the 8-bit pulse accumulators, pac3 and pac2, can be enabled only if paen in patcl ($a0) is cleared. if paen is set, pa3en and pa2en have no effect. the 8-bit pulse accumulators, pac1 and pac0, can be enabled only if pben in pbtcl ($b0) is cleared. if pben is set, pa1en and pa0en have no effect. paxen ? 8-bit pulse accumulator x enable bits 0 = 8-bit pulse accumulator disabled 1 = 8-bit pulse accumulator enabled 13.4.17 delay count er control register read: anytime write: anytime if enabled, after detection of a valid edge on input capture pin, the delay counter counts the pre-selected number of p clock (module clock) cycles, then it will generate a pulse on its output. the pulse is generated only if the level of input signal, after the preset delay, is the opposite of the level before the transition.this will avoid reaction to narrow input pulses. after counting, the counter will be cleared automatic ally. delay between two active edges of the input signal period should be longer t han the selected counter delay. dlyx ? delay counter select bits address: $00a8 bit 7654321bit 0 read: 0000pa3enpa2enpa1enpa0en write: reset:00000000 figure 13-37. input control pulse accumulators control register (icpacr) address: $00a9 bit 7654321bit 0 read: 000000dly1dly0 write: reset:00000000 figure 13-38. delay counter control register (dlyct) dly1 dly0 delay 0 0 disabled (bypassed) 0 1 256 p clock cycles 1 0 512 p clock cycles 1 1 1024 p clock cycles
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 182 freescale semiconductor 13.4.18 input contro l overwrite register read: anytime write: anytime an ic register is empty when it has been read or la tched into the holding register. a holding register is empty when it has been read. novwx ? no input capture overwrite bits 0 = the contents of the related capture register or holding register can be overwritten when a new input capture or latch occurs. 1 = the related capture register or holding regist er cannot be written by an event unless they are empty (see 13.3.1 ic channels ). this will prevent the captured value to be overwritten until it is read or latched in the holding register. 13.4.19 input control system control register read: anytime write: may be written once (smodn = 1). writes are always permitted when smodn = 0. shxy ? share input action of input capture channels x and y bits 0 = normal operation 1 = the channel input x causes the same action on the channel y. the port pin x and the corresponding edge detector is used to be active on the channel y. tfmod ? timer flag-setting mode bit use of the tfmod bit in the icsys register ($ab) in conjunction with the use of the icovw register ($aa) allows a timer interrupt to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture. address: $00aa bit 7654321bit 0 read: novw7 novw6 novw5 novw4 novw3 novw2 novw1 novw0 write: reset:00000000 figure 13-39. input control overwrite register (icovw) address: $00ab bit 7654321bit 0 read: sh37 sh26 sh15 sh04 tfmod pacmx bufen latq write: reset:00000000 figure 13-40. input control system control register (icsys)
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 183 by setting tfmod in queue mode, when novw bit is set and the corresponding capture and holding registers are emptied, an input capture event will firs t update the related input capture register with the main timer contents. at the next event, the tcn data is transferred to the tcnh register, the tcn is updated, and the cnf interrupt flag is set. see figure 13-19 . in all other input capture cases, the interrupt flag is set by a valid external event on ptn. 0 = the timer flags c3f?c0f in tflg1 ($8e) are set when a valid input capture transition on the corresponding port pin occurs. 1 = if in queue mode (bufen = 1 and latq = 0), the timer flags c3f?c0f in tflg1 ($8e) are set only when a latch on the corresponding holding register occurs. if the queue mode is not engaged, the timer flags c3f?c0f are set the same way as for tfmod = 0. pacmx ? 8-bit pulse accumulators maximum count bit 0 = normal operation. when the 8-bit pulse accumu lator has reached the value $ff, with the next active edge, it will be incremented to $00. 1 = when the 8-bit pulse accumulator has reached the value $ff, it will not be incremented further. the value $ff indicates a count of 255 or more. bufen ? ic buffer enable bit 0 = input capture and pulse accumulator holding registers are disabled. 1 = input capture and pulse accumulator holding registers are enabled. the latching mode is defined by latq control bit. writing a 1 into iclat bit in mcctl ($a6) when latq is set, will produce latching of input capture and pulse accu mulator registers into their holding registers. latq ? input control latch or queue mode enable bit the bufen control bit should be set to enable the ic and pulse accumulators? holding registers. otherwise, latq latching modes are disabled. writing one into iclat bit in mcctl ($a6), when latq and bufen are set will produce latching of input capture and pulse accumulators registers into their holding registers. 0 = queue mode of input capture is enabled. the main timer value is memorized in the ic register by a valid input pin transition. with a new occurr ence of a capture, the value of the ic register will be transferred to its holding register and the ic register memorizes the new timer value. 1 = latch mode is enabled. latching function occu rs when modulus down-count er reaches 0 or a 0 is written into the count register mccnt (see 13.3.1.2 buffered ic channels ). with a latching event the contents of ic registers and 8-bit pulse accumulators are transferred to their holding registers. the 8-bit pulse accumulators are cleared. 13.4.20 timer test register read: anytime write: only in special mode (smod = 1) address: $00ad bit 7654321bit 0 read:000000tcbyppcbyp (1) write: reset:00000000 = unimplemented 1. available only on mc68hc912b32 devices. figure 13-41. timer test register (timtst)
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 184 freescale semiconductor tcbyp ? main timer divider chain bypass bit 0 = normal operation 1 = for testing only. the 16-bit free-running timer counter is divided into two 8-bit halves and the prescaler is bypassed. the clock drives both halves directly. when the high byte of timer counter tcnt ($84) overflows from $ff to $00, the tof flag in tflg2 ($8f) will be set. 13.4.21 timer port data register read: anytime (input return pin level; outputs return data register contents) write: data stored in an internal latch (drives pins only if configured for output) since the output compare 7 register (oc7) shares pi ns with the pulse accumulator input, the only way for the pulse accumulator to receive an independent input from oc7 is by setting both om7 and ol7 to be 0, and also oc7m7 in oc7m register to be 0. oc7 can still reset the counter if enabled while pt7 is used as an input to the pulse accumulator. portt can be read anytime. when configured as an input, a read will return the pin level. when configured as an output, a read will return the latched output data. note writes do not change pin state when the pin is configured for timer output. the minimum pulse width for pulse a ccumulator input should always be greater than the width of two module clocks due to input synchronizer circuitry. the minimum pulse width for the input capture should always be greater than the width of two module clocks due to input synchronizer circuitry. 13.4.22 data direction register for timer port read: anytime write: anytime address: $00ae bit 7654321bit 0 read: pt7 pt6 pt5 pt4 pt3 pt2 pt1 pt0 write: timer: i/0c7 i/oc6 i/oc5 i/oc4 i/oc3 i/oc2 i/oc1 i/oc0 reset:00000000 figure 13-42. timer port data register (portt) address: $00af bit 7654321bit 0 read: ddt7 ddt6 ddt5 ddt4 ddt3 ddt2 ddt1 ddt0 write: reset:00000000 figure 13-43. data direction register for timer port (ddrt)
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 185 ddt[7:0] ? data direction bits for timer port the timer forces the i/o state to be an output for each timer port line associated with an enabled output compare. in these cases the data direction bits will not be changed, but have no effect on the direction of these pins. the ddrt will revert to controlling the i/o direction of a pin when the associated timer output compare is disabled. input captures do not override the ddrt settings. 0 = configures the corresponding i/o pin for input only 1 = configures the corresponding i/o pin for output 13.4.23 16-bit pulse accum ulator b control register read: anytime write: anytime sixteen-bit pulse accumulator b (pacb) is formed by cascading the 8-bit pulse accumulators pac1 and pac0. when pben is set, the pacb is enabled . the pacb shares the input pin with ic0. pben ? pulse accumulator b system enable bit pben is independent from ten. with timer disabled, the pulse accumu lator can still function unless pulse accumulator is disabled. 0 = 16-bit pulse accumulator system disabled. eight-bit pac1 and pac0 can be enabled when their related enable bits in icpacr ($a8) are set. 1 = pulse accumulator b system enabled. the two 8-bit pulse accumulators pac1 and pac0 are cascaded to form the pacb 16-bit pulse accumulator. when pacb is enabled, the pacn1 and pacn0 register contents are, respectively, the high and low byte of the pacb. pa1en and pa0en control bits in icpacr ($a8) have no effect. pbovi ? pulse accumulator b overflow interrupt enable bit 0 = interrupt inhibited 1 = interrupt requested if pbovf is set 13.4.24 pulse accumul ator b flag register read:anytime write:anytime address: $00b0 bit 7654321bit 0 read: 0pben0000pbov0 write: reset:00000000 figure 13-44. 16-bit pulse accumulator b control register (pbctl) address: $00b1 bit 7654321bit 0 read: 000000pbovf0 write: reset:00000000 figure 13-45. pulse accumulator b flag register (pbflg)
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 186 freescale semiconductor pbovf ? pulse accumulator b overflow flag this bit is set when the 16-bit pulse accumulator b overflows from $ffff to $0000 or when 8-bit pulse accumulator 1 (pac1) overflows from $ff to $00. this bit is cleared by a write to the pbflg register with bit 1 set. any access to the pacn1 and pacn0 r egisters will clear the pbovf flag in this register when tffca bit in register tscr ($86) is set. 13.4.25 8-bit pulse accum ulators holding registers read: anytime write: anytime these registers are used to latch the value of the corresponding pulse accumulator when the related bits in register icpacr ($a8) are enabled (see 13.3.2 pulse accumulators ). address: $00b2 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-46. 8-bit pulse accumulator holding register 3 (pa3h) address: $00b3 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-47. 8-bit pulse accumulator holding register 2 (pa2h) address: $00b4 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-48. 8-bit pulse accumulator holding register 1 (pa1h) address: $00b5 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-49. 8-bit pulse accumulator holding register 0 (pa0h)
timer registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 187 13.4.26 modulus down-c ounter count registers read: anytime write: anytime a full access for the counter register should take pl ace in one clock cycle. a separate read/write for high byte and low byte will give different results than accessing them as a word. if the rdmcl bit in mcctl register is cleared, reads of the mccnt register will re turn the present value of the count register. if the rdmcl bit is set, reads of the mccnt will return the contents of the load register. if a $0000 is written into mccnt a nd modulus counter while latq and bufen in icsys ($ab) register are set, the input capture and pulse accumulator registers will be latched. with a $0000 write to the mccnt, the modulus counter will stay at 0 and does not set the mczf flag in mcflg register. if modulus mode is enabled (modmc = 1), a write to this address will update the load register with the value written to it. the count register will not be updated with the new value until the next counter underflow. the flmc bit in mcctl ($a6) can be used to immediately update the count register with the new value if an immediate load is desired. if modulus mode is not enabled (modmc = 0), a write to this address will clear the prescaler and will immediately update the counter register with the value written to it and down-counts once to $0000. 13.4.27 timer input c apture holding registers address: $00b6 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $00b7 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 13-50. modulus down-co unter count registers (mccnt) address: $00b8 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $00b9 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-51. timer input capture holding register 0 (tc0h)
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 188 freescale semiconductor read: anytime write: has no effect these registers are used to latch the value of the input capture registers tc0?tc3. the corresponding iosx bits in tios ($80) should be cleared (see 13.3.1 ic channels ). address: $00ba bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $00bb bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-52. timer input capture holding register 1 (tc1h) address: $00bc bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $00bd bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-53. timer input capture holding register 2 (tc2h) address: $00be bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $00bf bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 13-54. timer input capture holding register 3 (tc3h)
timer and modulus counter operation in different modes m68hc12b family data sheet, rev. 9.1 freescale semiconductor 189 13.5 timer and modulus counte r operation in different modes stop timer and modulus counter are off since clocks are stopped. bgdm timer and modulus counter keep on running unless bit 5, tsbck, of tscr is set to 1. see 13.4.6 timer system control register . wait counters keep on running, unless the ts wai bit in tscr is set to 1. see 13.4.6 timer system control register . normal timer and modulus counter keep on running, unl ess the ten bit in tscr and mcen in mcctl, respectively, are cleared. see 13.4.6 timer system control register and 13.4.14 16-bit modulus down-counter control register . ten = 0 all 16-bit timer operations are stopped; can only access the registers mcen = 0 modulus counter is stopped. paen = 1 sixteen-bit pulse accumulator a is active. paen = 0 eight-bit pulse accumulators 3 and 2 can be enabled. see 13.4.16 input control pulse accumulators control register . pben = 1 sixteen-bit pulse accumulator b is active. pben = 0 eight-bit pulse accumulators 1 and 0 can be enabled. see 13.4.16 input control pulse accumulators control register .
enhanced capture timer (ect) module m68hc12b family data sheet, rev. 9.1 190 freescale semiconductor
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 191 chapter 14 serial interface 14.1 introduction the serial interface of the mcu consists of two independent serial input/output (i/o) subsystems: serial communication interface (sci) serial peripheral interface (spi) each serial pin shares function with the gener al-purpose port pins of port s. the sci is an nrz (non-return to zero) type system that is compatible with standard rs-232 systems. the sci system has a single-wire operation mode which allows the unused pin to be available as general-purpose i/o. the spi subsystem, which is compatible with the m68hc11 spi, includes new features such as ss output and bidirectional mode. figure 14-1. serial interface block diagram sci i/o spi ddrs/ioctlr port s i/o drivers serial interface ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 rxd txd miso/siso mosi/momi sck cs /ss i/o i/o
serial interface m68hc12b family data sheet, rev. 9.1 192 freescale semiconductor 14.2 serial communic ation interface (sci) the sci on the mcu is an nrz format (one start, eight or nine data, and one stop bit) asynchronous communication system with independent internal baud rate generation circuitry and an sci transmitter and receiver. it can be configured for eight or nine data bits (one of which may be designated as a parity bit, odd or even). if enabled, parity is generated in hard ware for transmitted and received data. receiver parity errors are flagged in hardware. the baud rate generator is based on a modulus counter, allowing flexibility in choosing baud rates. there is a receiv er wakeup feature, an idle line detect feature, a loop-back mode, and various error detection features. two port pins provide the external interface for the transmitted data (txd) and the received data (rxd). see figure 14-2 . figure 14-2. serial communications interface block diagram rx baud rate tx baud rate mclk divider 10-11 bit shift reg msb txd buffer/sc0drl txmtr control sc0cr2/sci ctl 2 sc0cr1/sci ctl 1 sc0sr1/int status data recovery 10-11 bit shift reg rxd buffer/sc0drl sc0bd/select lsb rxd txd pin control / ddrs / port s wakeup logic sc0cr1/sci ctl 1 sc0sr1/int status sc0cr2/sci ctl 2 int request logic msb lsb int request logic sci receiver sci transmitter data bus parity detect parity generator to internal logic baud rate clock ps0 ps1
serial communication interface (sci) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 193 14.2.1 data format the serial data format requires these conditions: an idle-line in the high state before transmission or reception of a message a start bit (logic 0), transmitted or received , that indicates the start of each character data that is transmitted or received least significant bit (lsb) first a stop bit (logic 1) used to indicate the end of a frame a frame consists of: a start bit a character of eight or nine data bits a stop bit a break is defined as the transmission or reception of a logic 0 for one frame or more. this sci supports hardware parity for transmit and receive. 14.2.2 sci baud rate generation the basis of the sci baud rate generator is a 13-bit modulus counter. this counter gives the generator the flexibility necessary to achieve a reasonable level of independence from the cpu operating frequency and still be able to produce standard baud rates with a minimal amount of error. the clock source for the generator comes from the p clock. table 14-1. baud rate generation desired sci baud rate br divisor for p = 4.0 mhz br divisor for p = 8.0 mhz 110 2273 4545 300 833 1667 600 417 833 1200 208 417 2400 104 208 4800 52 104 9600 26 52 14,400 17 35 19,200 13 26 38,400 ? 13
serial interface m68hc12b family data sheet, rev. 9.1 194 freescale semiconductor 14.2.3 sci regist er descriptions control and data registers for the sci subsystem are described here. the memory address indicated for each register is the default address that is in use after reset. the entire 512-byte register block can be mapped to any 2-kbyte boundary within the standard 64-kbyte address space. 14.2.3.1 sci baud rate control register read: anytime write: sbr12?sbr0 anytime; low-order byte must be written for change to take effect ? sbr15?sbr13 only in special modes sc0bdh and sc0bdl are considered together as a 16-bit baud rate control register. the value in sbr12?sbr0 determines the baud rate of the sci. the desired baud rate is determined by the following formula: which is equivalent to: br is the value written to bits sbr12?sbr0 to establish the baud rate. note the baud rate generator is disabled until the te or re bit in sc0cr2 register is set for the first time after reset and/or the baud rate generator is disabled when sbr12?sbr0 = 0. btst ? reserved for test function bspl ? reserved for test function brld ? reserved for test function address: $00c0 bit 7654321bit 0 read: btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 write: reset:00000000 figure 14-3. sci baud rate control register (sc0bdh) address: $00c1 bit 7654321bit 0 read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: reset:00000100 figure 14-4. sci baud rate control register (sc0bdl) sci baud rate mclk 16 br --------------------- = br mclk 16 sci baud rate ------------------------------------------------- - =
serial communication interface (sci) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 195 14.2.3.2 sci control register 1 read: anytime write: anytime loops ? sci loop mode/single-wire mode enable bit 0 = sci transmit and receive sections operate normally. 1 = sci receive section is disconnected from th e rxd pin and the rxd pin is available as general-purpose i/o. the receiver input is determined by the rsrc bit. the transmitter output is controlled by the associated ddrs bit. both the transmitter and the receiver must be enabled to use the loop or the single-wire mode. if the ddrs bit associated with the txd pin is set during the loops = 1, the txd pin outputs the sci waveform. if the ddrs bit associated with the txd pin is clear during the loops = 1, the txd pin becomes high (idle line state) for rsrc = 0 and high impedance for rsrc = 1. refer to table 14-2 . woms ? wired-or mode for serial pins this bit controls the two pins (txd and rxd) associated with the scix section. 0 = pins operate in a normal mode with both high and low drive capability. to affect the rxd bit, that bit would have to be configured as an output (via dds0/2) which is the single-wire case when using the sci. woms bit still affects general-purpose output on txd and rxd pins when scix is not using these pins. 1 = each pin operates in an open drain fashion if that pin is declared as an output . address: $00c2 bit 7654321bit 0 read: loops woms rsrc m wake ilt pe pt write: reset:00000000 figure 14-5. sci control register 1 (sc0cr1) table 14-2. loop mode functions loop s rsr c dds1 wom s function of port s bit 1/3 0 x x x normal operations 1000/1 loop mode without txd output (txd = high impedance) 1 0 1 0 loop mode with txd output (cmos) 1 0 1 1 loop mode with txd output (open-drain) 110 x single-wire mode without txd output (pin is used as receiver input only, txd = high impedance) 111 0 single-wire mode with txd output (the output is also fed back to receiver input, cmos.) 111 1 single wire mode for the receiving and transmitting (open-drain)
serial interface m68hc12b family data sheet, rev. 9.1 196 freescale semiconductor rsrc ? receiver source bit when loops = 1, the rsrc bit determines the internal feedback path for the receiver. 0 = receiver input connected to the transmitter internally (not txd pin) 1 = receiver input connected to the txd pin m ? mode bit (select character format) 0 = one start, eight data, one stop bit 1 = one start, eight data, ninth data, one stop bit wake ? wakeup by address mark/idle bit 0 = wakeup by idle line recognition 1 = wakeup by address mark (last data bit set) ilt ? idle line type bit this bit determines which of two types of id le line detection is used by the sci receiver. 0 = short idle line mode enabled 1 = long idle line mode detected in short mode, the sci circuitry begins counting 1s in the search for the idle line condition immediately after the start bit. this means that the stop bit and any bits that were 1s before the stop bit could be counted in that string of 1s, resulting in earlier recognition of an idle line. in long mode, the sci circuitry does not begin counting 1s in the search for the idle line condition until a stop bit is received. therefore, the last byte?s st op bit and preceding 1 bits do not affect how quickly an idle line condition can be detected. pe ? parity enable bit 0 = parity disabled 1 = parity enabled pt ? parity type bit if parity is enabled, this bit determ ines even or odd parity for both the receiver and the transmitter. an even number of 1s in the data character causes t he parity bit to be 0 and an odd number of 1s causes the parity bit to be 1. 0 = even parity selected 1 = odd parity selected
serial communication interface (sci) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 197 14.2.3.3 sci control register 2 read: anytime write: anytime tie ? transmit interrupt enable bit 0 = tdre interrupts disabled 1 = sci interrupt requested when tdre status flag is set tcie ? transmit complete interrupt enable bit 0 = tc interrupts disabled 1 = sci interrupt requested when tc status flag is set rie ? receiver interrupt enable bit 0 = rdrf and or interrupts disabled 1 = sci interrupt requested when rdrf status flag or or status flag is set ilie ? idle line interrupt enable bit 0 = idle interrupts disabled 1 = sci interrupt requested when idle status flag is set te ? transmitter enable bit 0 = transmitter disabled 1 = sci transmit logic is enabled and the txd pin (port s bit 1) is dedicated to the transmitter. t he te bit can be used to queue an idle preamble. re ? receiver enable bit 0 = receiver disabled 1 = enables the sci receive circuitry rwu ? receiver wakeup control bit 0 = normal sci receiver 1 = enables the wakeup function and i nhibits further receiver interrupts. normally, hardware wakes the receiver by automatically clearing this bit. sbk ? send break bit 0 = break generator off 1 = generate a break code, at least 10 or 11 contiguous 0s. as long as sbk remains set, the transmitter s ends 0s. when sbk is changed to 0, the current frame of all 0s is finished before the txd line goes to the idle state. if sbk is toggled on and off, the transmitter sends only 10 (or 11) 0s and then reverts to mark idle or sending data. address: $00c3 bit 7654321bit 0 read: tie tcie rie ilie te re rwu sbk write: reset:00000000 figure 14-6. sci control register 2 (sc0cr2)
serial interface m68hc12b family data sheet, rev. 9.1 198 freescale semiconductor 14.2.3.4 sci status register 1 read: anytime; used in auto clearing mechanism write: has no meaning or effect the bits in these registers are set by various condit ions in the sci hardware and are cleared automatically by special acknowledge s equences. the receive related flag bits in sc0sr1 (rdrf, idle, or, nf, fe, and pf) are all cleared by a read of the sc0sr1 regi ster followed by a read of the transmit/receive data register low byte. however, only those bits which were set when sc0sr1 was read will be cleared by the subsequent read of the transmit/receive data register low byte. the transmit related bits in sc0sr1 (tdre and tc) are cleared by a read of the sc0sr1 r egister followed by a write to the transmit/receive data register low byte. tdre ? transmit data register empty flag new data is not transmitted unless sc0sr1 is read before writing to the transmit data register. reset sets this bit. 0 = sc0dr busy 1 = any byte in the transmit data register is transferred to the serial shift register so new data may now be written to the transmit data register. tc ? transmit complete flag flag is set when the transmi tter is idle (no data, preamble, or br eak transmission in progress). clear by reading sc0sr1 with tc set and then writing to sc0dr. 0 = transmitter busy 1 = transmitter idle rdrf ? receive data register full flag once cleared, idle is not set again until the rx d line has been active and becomes idle again. rdrf is set if a received character is ready to be read from sc0dr. clear the rdrf flag by reading sc0sr1 with rdrf set and then reading sc0dr. 0 = sc0dr empty 1 = sc0dr full idle ? idle line detected flag receiver idle line is detected (the receipt of a minimum of 10 or 11 consecutive 1s). this bit is not set by the idle line condition when the rwu bit is set. once cleared, idle is not set again until after rdrf has been set (after the line has been active and becomes idle again). 0 = rxd line active 1 = rxd line idle address: $00c4 bit 7654321bit 0 read: tdre tc rdrf idle or nf fe pf write: reset:11000000 = unimplemented figure 14-7. sci status register 1 (sc0sr1)
serial communication interface (sci) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 199 or ? overrun error flag new byte is ready to be transferred from the receive shift register to the receive data register and the receive data register is already full (rdrf bit is se t). data transfer is inhibited until this bit is cleared. 0 = no overrun 1 = overrun detected nf ? noise error flag set during the same cycle as the rdrf bit but not set in the case of an overrun (or). 0 = unanimous decision 1 = noise on a valid start bit, any of the data bits, or on the stop bit fe ? framing error flag set when a 0 is detected where a stop bit was expected. clear the fe flag by reading sc0sr1 with fe set and then reading sc0dr. 0 = stop bit detected 1 = zero detected rather than a stop bit pf ? parity error flag indicates if received data?s parity matches parity bit. this feature is active only when parity is enabled. the type of parity tested for is determined by the pt (parity type) bit in sc0cr1. 0 = parity correct 1 = incorrect parity detected 14.2.3.5 sci status register 2 read: anytime write: has no meaning or effect raf ? receiver active flag this bit is controlled by the receiver front end. it is set during the rt1 time period of the start bit search. it is cleared when an idle state is detected or when the receiver circuitry detects a false start bit (generally due to noise or baud rate mismatch). 0 = character is not being received. 1 = character is being received. address: $00c5 bit 7654321bit 0 read:0000000raf write: reset:00000000 = unimplemented figure 14-8. sci status register 2 (sc0sr2)
serial interface m68hc12b family data sheet, rev. 9.1 200 freescale semiconductor 14.2.3.6 sci data register read: anytime write: varies on a bit by bit basis r8 ? receive bit 8 write has no meaning or effect. this bit is the ninth serial data bit received when t he sci system is configured for 9-data-bit operation. t8 ? transmit bit 8 write anytime. this bit is the ninth serial data bit transmitted when the sci system is configured for 9-data-bit operation. when using 9-bit data format, this bit does not have to be written for each data word. the same value is transmitted as the ninth bit until this bit is rewritten. r7t7?r0t0 ? receive/transmit data bits 7 to 0 reads access the eight bits of the read-only sci receive data register (rdr). writes access the eight bits of the write-only sci transmit data register (tdr). sc0drl and sc0drh form the 9-bit data word for the sci. if the sci is being used with a 7- or 8-bit data word, only sc0drl needs to be accessed. if a 9-bit format is used, the upper register should be wr itten first to ensure that it is transferred to the transmitter shift register with the lower register. address: $00c6 bit 7654321bit 0 read: r8 t8 000000 write: reset:uu000000 = unimplemented u = unaffected figure 14-9. sci data register high (sc0drh) address: $00c7 bit 7654321bit 0 read: r7t7 r6t6 r5t5 r4t4 r3t3 r2t2 r1t1 r0t0 write: reset: unaffected by reset figure 14-10. sci data register low (sc0drl)
serial peripheral interface (spi) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 201 14.3 serial peripheral interface (spi) the serial peripheral interface (spi) allows the mcu to communicate synchronously with peripheral devices and other microprocessors. the spi system in the mcu can operate as a master or as a slave. the spi is also capable of interprocessor communications in a multiple master system. when the spi is enabled, all pins that are defined by the configuration as inputs will be inputs regardless of the state of the ddrs bits for those pins. all pins that are defined as spi outputs will be outputs only if the ddrs bits for those pins are set. any spi out put whose corresponding ddrs bit is cleared can be used as a general-purpose input. a bidirectional serial pin is possible using the ddrs as the direction control. figure 14-11. serial peripheral interface block diagram pin control logic 8-bit shift register read data buffer shift control logic clock logic spi control sp0sr spi status register sp0dr spi data register spif wcol modf divider select sp0br spi baud rate register 2 4 8 16 32 64 128 256 spi interrupt internal bus mcu p clock same as e rate s m m s m s spr2 spr1 spr0 request spie spe mstr cpol cpha lsbf lsbf pups rds swom spc0 ssoe spe clock mstr swom miso ps4 sck ps6 ss ps7 mosi ps5 sp0cr1 spi control register 1 sp0cr2 spi control register 2
serial interface m68hc12b family data sheet, rev. 9.1 202 freescale semiconductor 14.3.1 spi baud rate generation the p clock is input to a divider series and the re sulting spi clock rate may be selected to be p divided by 2, 4, 8, 16, 32, 64, 128, or 256. three bits in the sp0br register control the spi clock rate. this baud rate generator is activated only when spi is in the master mode and serial transfer is taking place. otherwise, this divider is disabled to save power. 14.3.2 spi operation in the spi system, the 8-bit data register in the mast er and the 8-bit data register in the slave are linked to form a distributed 16-bit register. when a data trans fer operation is performed, this 16-bit register is serially shifted eight bit positions by the sck clock from the master so the data is effectively exchanged between the master and the slave. data written to the sp0dr register of the master becomes the output data for the slave and data read from the sp0dr regist er of the master after a transfer operation is the input data from the slave. a clock phase control bit (cpha) an d a clock polarity control bit (cpol) in the spi control register 1 (sp0cr1) select one of four possible clock formats to be used by the spi system. the cpol bit simply selects non-inverted or inverted clock. the cpha bit is used to accommodate two fundamentally different protocols by shifting the clock by one half cycle or no phase shift. figure 14-12. spi clock format 0 (cpha = 0) t l begin end sck (cpol = 0) sample i change o transfer sck (cpol = 1) msb first (lsbf = 0) : lsb first (lsbf = 1) : msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o mosi pin miso pin mosi/miso t t f or t t , t l , t l minimum 1/2 sck t i t l sel ss (o) sel ss (i) master only
serial peripheral interface (spi) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 203 figure 14-13. spi clock format 1 (cpha = 1) 14.3.3 ss output available in master mode only, ss output is enabled with the ssoe bit in the sp0cr1 register if the corresponding ddrs bit is set. the ss output pin is connected to the ss input pin of the external slave device. the ss output automatically goes low for each transmission to select the external device and it goes high during each idling state to deselect external devices. table 14-3. ss output selection dds7 ssoe master mode slave mode 00ss input with modf feature ss input 01reserved ss input 1 0 general-purpose output ss input 11ss output ss input t l t t for t t , t l , t l minimum 1/2 sck t i t l begin end sck (cpol = 0) sample i change o sel ss (o) transfer sck (cpol = 1) msb first (lsbf= 0) : lsb first (lsbf = 1) : msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change o sel ss (i) mosi pin miso pin master only mosi/miso
serial interface m68hc12b family data sheet, rev. 9.1 204 freescale semiconductor 14.3.4 bidirectional mode (momi or siso) in bidirectional mode, the spi uses only one serial data pin for external device interface. the mstr bit decides which pin to be used. the mosi pin becomes a serial data i/o (momi) pin for the master mode, and the miso pin becomes a serial data i/o (siso) pin for the slave mode. the direction of each serial i/o pin depends on the corresponding ddrs bit. figure 14-14. normal mode and bidirectional mode 14.3.5 spi regist er descriptions control and data registers for the spi subsystem ar e described in this section. the memory address indicated for each register is the default address that is in use after reset. the entire 512-byte register block can be mapped to any 2-kbyte boundary within the standard 64-kbyte address space. for more information, refer to chapter 5 operating modes and resource mapping . 14.3.5.1 spi control register 1 read: anytime write: anytime spie ? spi interrupt enable bit 0 = spi interrupts are inhibited. 1 = hardware interrupt sequence is requested each time the spif or modf status flag is set. when spe = 1 master mode mstr = 1 slave mode mstr = 0 normal mode spc0 = 0 swom enables open-drain output. swom enables open-drain output. bidirectional mode spc0 = 1 swom enables open-drain output. ps4 becomes gpio . swom enables open-drain output. ps5 becomes gpio. address: $00d0 bit 7654321bit 0 read: spie spe swom mstr cpol cpha ssoe lsbf write: reset:00000100 figure 14-15. spi control register 1 (sp0cr1) spi mo mi dds5 serial out serial in spi si so serial in serial out dds4 spi momi ps4 dds5 serial out serial in spi ps5 siso dds4 serial in serial out
serial peripheral interface (spi) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 205 spe ? spi system enable bit 0 = spi internal hardware is initialized and spi system is in a low-power disabled state. 1 = ps4?ps7 are dedicated to the spi function. when modf is set, spe always reads 0. sp0cr1 mu st be written as part of a mode fault recovery sequence. swom ? port s wired-or mode bit controls not only spi output pins but also the general-purpose output pins (ps4?ps7) which are not used by spi. 0 = spi and/or ps4?ps7 output buffers operate normally. 1 = spi and/or ps4?ps7 output buffers behave as open-drain outputs. mstr ? spi master/slave mode select bit 0 = slave mode 1 = master mode cpol and cpha ? spi clock polarity, clock phase bits these two bits are used to specify the clock format to be used in spi operations. when the clock polarity bit is cleared and data is not being transferr ed, the sck pin of the master device is low. when cpol is set, sck idles high. see figure 14-12 and figure 14-13 . ssoe ? slave select output enable bit the ss output feature is enabled only in master mode by asserting the ssoe and dds7. lsbf ? spi lsb first enable bit 0 = data is transferred most-s ignificant bit (msb) first. 1 = data is transferred least- significant bit (lsb) first. normally, data is transferred msb first. this bit does not affect the position of the msb and lsb in the data register. reads and writes of the da ta register always have msb in bit 7. 14.3.5.2 spi control register 2 read: anytime write: anytime pups ? pullup port s enable bit 0 = no internal pullups on port s 1 = all port s input pins have an active pullup device. if a pin is programmed as output, the pullup device becomes inactive. rds ? reduce drive of port s bit 0 = port s output drivers operate normally. 1 = all port s output pins have reduced drive capability for lower power and less noise. address: $00d1 bit 7654321bit 0 read: 0 0 0 0 pups rds 0 spc0 write: reset:00001000 = unimplemented figure 14-16. spi control register 2 (sp0cr2)
serial interface m68hc12b family data sheet, rev. 9.1 206 freescale semiconductor spc0 ? serial pin control 0 bit this bit decides serial pin configurations with mstr control bit. 14.3.5.3 spi baud rate register read: anytime write: anytime at reset, e clock divided by 2 is selected. spr2?spr0 ? spi clock (sck) rate select bits these bits are used to specify the spi clock rate. table 14-4. serial pin control pin mode spc0 (1) 1. the serial pin control 0 bit enables bidirectional configurations. mstr miso (2) 2. slave output is enabled if dds4 = 1, ss = 0, and mstr = 0. (#1, #3) mosi (3) 3. master output is enabled if dds5 = 1 and mstr = 1. (#2, #4) sck (4) 4. sck output is enabled if dds6 = 1 and mstr = 1. (#2, #4) ss (5) 5. ss output is enabled if dds7 = 1, sso e = 1, and mstr = 1. (#2, #4) #1 normal 0 0 slave out slave in sck in ss in #2 1 master in master out sck out ss i/o #3 bidirectional 1 0 slave i/o general-purposei/o sck in ss in #4 1 general-purposei/o master i/o sck out ss i/o address: $00d2 bit 7654321bit 0 read:00000 spr2 spr1 spr0 write: reset:00000000 = unimplemented figure 14-17. spi baud rate register (sp0br) table 14-5. spi clock rate selection spr2 spr1 spr0 e clock divisor frequency at e clock = 4 mhz frequency at e clock = 8 mhz 0 0 0 2 2.0 mhz 4.0 mhz 0 0 1 4 1.0 mhz 2.0 mhz 0 1 0 8 500 khz 1.0 mhz 0 1 1 16 250 khz 500 khz 1 0 0 32 125 khz 250 khz 1 0 1 64 62.5 khz 125 khz 1 1 0 128 31.3 khz 62.5 khz 1 1 1 256 15.6 khz 31.3 khz
serial peripheral interface (spi) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 207 14.3.5.4 spi status register read: anytime write: has no meaning or effect spif ? spi interrupt request bit spif is set after the eighth sck cycle in a data transfe r, and it is cleared by reading the sp0sr register (with spif set) followed by an access (read or write) to the spi data register. wcol ? write collision status flag the mcu write is disabled to avoid writing over the data being transferred. no interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the time of the error. this bit is cleared automatically by a read of the sp0sr (with wcol set) followed by an access (read or write) to the sp0dr register. 0 = no write collision 1 = indicates that a serial transfer was in progress when the mcu tried to write new data into the sp0dr data register modf ? spi mode error interrupt status flag this bit is set automatically by spi hardware, if t he mstr control bit is set and the slave select input pin becomes 0. this condition is not permitted in normal operation. in the case where ddrs bit 7 is set, the ps7 pin is a general-purpose output pin or ss output pin rather than being dedicated as the ss input for the spi system. in this special case , the mode fault function is inhibited and modf remains cleared. this flag is cleared automatically by a read of the sp0sr (with modf set) followed by a write to the sp0cr1 register. 14.3.5.5 spi data register read: anytime; normally, only after spif flag set write: anytime; see wcol write collision flag in 14.3.5.4 spi status register this 8-bit register is both the input and output register for spi data. reads of this register are double buffered but writes cause data to bewritten directly into the serial shifter. in the spi system, the 8-bit data register in the master and the 8-bit data register in the slave are linked by the mosi and miso wires to address: $00d3 bit 7654321bit 0 read:spifwcol0modf0000 write: reset:00000000 = unimplemented figure 14-18. spi status register (sp0sr) address: $00d5 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset figure 14-19. spi data register (sp0dr)
serial interface m68hc12b family data sheet, rev. 9.1 208 freescale semiconductor form a distributed 16-bit register. when a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the sck clock from the master so the data is exchanged effectively between the master and the slave. note some slave devices are simple and either accept data from the master without returning data to the master or pass data to the master without requiring data from the master. 14.4 port s in all modes, port s bits ps7?ps0 can be used for either general-purpose i/o or with the sci and spi subsystems. during reset, port s pins are config ured as high-impedance inputs (ddrs is cleared). 14.4.1 port s data register read: anytime; inputs return pin level; outputs return pin driver input level write: data stored in internal latch; drives pins only if configured for output; does not change pin state when pin configured for spi or sci output port s shares function with the on-chip serial systems, spi0 and sci0. 14.4.2 port s data direction register read: anytime write: anytime after reset, all general-purpose i/o are configured for input only. 0 = configure the corresponding i/o pin for input only. 1 = configure the corresponding i/o pin for output. address: $00d6 bit 7654321bit 0 read: ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 write: pin function ss cs sck mosi momi miso siso ? ? txd0 rxd0 reset: after reset all bits configured as general-purpose inputs figure 14-20. port s data register (ports) address: $00d7 bit 7654321bit 0 read: dds7 dds6 dds5 dds4 dds3 dds2 dds1 dds0 write: reset:00000000 figure 14-21. port s data direction register (ddrs)
port s m68hc12b family data sheet, rev. 9.1 freescale semiconductor 209 dds0 ? data direction for port s bit 0 if the sci receiver is configured for 2-wire sc i operation, corresponding port s pins are input regardless of the state of these bits. dds1 ? data direction for port s bit 1 if the sci transmitter is configured for 2-wire sci operation, corresponding port s pins are output regardless of the state of these bits. dds2 and dds3 ? data direction for port s bit 2 and bit 3 these bits are for general-purpose only. dds6?dds4 ? data direction for port s bits 6?4 if the spi is enabled and expects the corresponding port s pin to be an input, it will be an input regardless of the state of the ddrs bit. if the spi is enabled and expects the bit to be an output, it will be an output only if the ddrs bit is set. dds7 ? data direction for port s bit 7 in spi slave mode, dds7 has no meaning or e ffect; the ps7 pin is dedicated as the ss input. in spi master mode, dds7 determines whether ps7 is an error detect input to the spi or a general-purpose or slave select output line. 14.4.3 pullup and reduced drive regist er for port s read: anytime write: anytime rdps2 ? reduce drive of ps7?ps4 0 = port s output drivers for bits 7?4 operate normally. 1 = port s output pins for bits 7?4 have reduced drive capability for lower power and less noise. rdps1 ? reduce drive of ps3 and ps2 0 = port s output drivers for bits 3 and 2 operate normally. 1 = port s output pins for bits 3 and 2 have redu ced drive capability for lower power and less noise. rdps0 ? reduce drive of ps1 and ps0 0 = port s output drivers for bits 1 and 0 operate normally. 1 = port s output pins for bits 1 and 0 have redu ced drive capability for lower power and less noise. pups2 ? pullup port s enable ps7?ps4 0 = no internal pullups on port s bits 7?4. 1 = port s input pins for bits 7?4 have an active pullup device. if a pin is programmed as output, the pullup device becomes inactive. address: $00db bit 7654321bit 0 read: 0 rdps2 rdps1 rdps0 0 pups2 pups1 pups0 write: reset:00000000 = unimplemented figure 14-22. pullup and reduced drive register for port s (purds)
serial interface m68hc12b family data sheet, rev. 9.1 210 freescale semiconductor pups1 ? pullup port s enable ps3 and ps2 bit 0 = no internal pullups on port s bits 3 and 2 1 = port s input pins for bits 3 and 2 have an active pullup device. if a pin is programmed as output, the pullup device becomes inactive. pups0 ? pullup port s enable ps1 and ps0 bit 0 = no internal pullups on port s bits 1 and 0 1 = port s input pins for bits 1 and 0 have an active pullup device. if a pin is programmed as output, the pullup device becomes inactive. 14.5 serial character tr ansmission using the sci code is intended to use sci1 to serially transmit characters usi ng polling to the lcd display on the udlp1 board: when the transmission data register is empty a flag will get set, which is telling us that sc1dr is ready so we can write another byte. the transmission is performed at a baud rate of 9600. since the sci1 is only being used for transmit data, the data register wi ll not be used bidirectionally for received data. 14.5.1 equipment for this exercise, use the m6 8hc912b32evb emulation board. 14.5.2 code listing note a comment line is deliminted by a se mi-colon. if there is no code before comment, an ?;? must be placed in the first column to avoid assembly errors. include 'equates.asm' ; equates for registers ; user variables ; bit equates ; ---------------------------------------------------------------------- ; main program ; ---------------------------------------------------------------------- org $7000 ; 16k on-board ram, user code data area, ; ; start main program at $4000 main: bsr init ; subroutine to initialize sci0 registers bsr trans ; subroutine to start transmission done: bra done ; always branch to done, convenient for breakpoint ; ---------------------------------------------------------------------- ; subroutine init: ; ---------------------------------------------------------------------- init: tpa ; transfer ccr to a accumulator oraa #$10 ; ored a with #$10 to set i bit tap ; transfer a to ccr movb #$34,sc1bdl ; set baud =9600, in sci1 baud rate reg. movb #$00,sc1cr1 ; initialize for 8-bit data format, ; ; loop mode and parity disabled,(sc1cr1)
synchronous character transmission using the spi m68hc12b family data sheet, rev. 9.1 freescale semiconductor 211 movb #$08,sc1cr2 ; set for no ints, and transmitter enabled(sc1cr2) ldaa sc1sr1 ; 1st step to clear tdre flag: read sc1sr1 std sc1drh ; 2nd step to clear tdre flag: write sc1dr register ldx #data ; use x as a pointer to data. rts ; return from subroutine ; ---------------------------------------------------------------------- ; transmit subroutine ; ---------------------------------------------------------------------- trans: brclr sc1sr1,#$80, trans ; wait for tdre flag movb 1,x+,sc1drl ; transmit character, increment x pointer cpx #eot ; detect if last character has been transmitted bne trans ; if last char. not equal to "eot", branch to trans rts ; else transmission complete, return from subroutine ; ---------------------------------------------------------------------- ; table : data to be transmitted ; ---------------------------------------------------------------------- data: dc.b 'freescale hc12 banner - june, 1999' dc.b $0d,$0a ; return (cr) ,line feed (lf) dc.b 'scottsdale, arizona' dc.b $0d,$0a ; return (cr) ,line feed (lf) eot: dc.b $04 ; byte used to test end of data = eot end ; end of program 14.6 synchronous character transmission using the spi this program is intended to communicate with the hc11 on the udlp1 board. it utilizes the spi to transmit synchronously characters in a string to be displayed on the lcd display. the program must configure the spi as a master, and non-interrupt driv en. the slave peripheral is chip-selected with the ss line at low voltage level. between 8 bit transfers the ss line is held high. also the clock idles low and takes data on the rising clock edges. the serial clock is set not to exceed 100 khz baud rate. 14.6.1 equipment for this exercise, use the m6 8hc912b32evb emulation board. 14.6.2 code listing note a comment line is deliminted by a se mi-colon. if there is no code before comment, an ?;? must be placed in the first column to avoid assembly errors.
serial interface m68hc12b family data sheet, rev. 9.1 212 freescale semiconductor include 'equates.asm' ;equates for all registers ; user variables ; bit equates ; ---------------------------------------------------------------------- ; main program ; ---------------------------------------------------------------------- org $7000 ; 16k on-board ram, user code data area, ; ; start main program at $7000 main: bsr init ; subroutine to initialize spi registers bsr transmit ; subroutine to start transmission finish: bra finis ; finished transmitting all data ; ---------------------------------------------------------------------- ;* subroutine init: ; ---------------------------------------------------------------------- init: bset ports,#$80 ; set ss line high to prevent glitch movb #$e0,ddrs ; configure port s input/ouput levels ; ; mosi, sck, ss* = ouput, miso=input movb #$07,sp0br ; select serial clock baud rate < 100 khz movb #$12,sp0cr1 ; configure spi(sp0cr1): no spi interrupts, ; ; mstr=1, cpol=0, cpha=0 movb #$08,sp0cr2 ; config. ports output drivers to operate normally, ; ; and with active pull-up devices. ldx #data ; use x register as pointer to first character ldaa sp0sr ; 1st step to clear spif flag, read sp0sr ldaa sp0dr ; 2nd step to clear spif flag, access sp0dr bset sp0cr1,#$40 ; enable the spi (spe=1) rts ; return from subroutine ; ---------------------------------------------------------------------- ;* transmit subroutine ; ---------------------------------------------------------------------- transmit: ldaa 1,x+ ; load acc. with "new" character to send, inc x beq done ; detect if last character(0) has been transmitted ; ; if last char. branch to done, else bclr ports,#$80 ; assert ss line to start x-misssion. staa sp0dr ; load data into data reg.,x-mit. ; ; it is also the 2nd step to clear spif flag. flag: brclr sp0sr,#$80,flag ;wait for flag. bset ports,#$80 ; disassert ss line. bra transmit ; continue sending characters, branch to transmit. done: rts ; return from subroutine ; ---------------------------------------------------------------------- ; table of data to be transmitted ; ---------------------------------------------------------------------- data: dc.b 'freescale' dc.b $0d,$0a ; return (cr) ,line feed (lf) eot: dc.b $00 ; byte used to test end of data = eot end ; end of program
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 213 chapter 15 byte data link communications (bdlc) 15.1 introduction the byte data link communications module (bdlc) prov ides access to an external serial communication multiplex bus, operating according to the sae j1850 protocol. 15.2 features features of the bdlc module include: sae j1850 class b data communi cations network interface compatible and iso compatible for low-speed (< 125 kbps) serial data communicatio ns in automotive applications 10.4 kbps variable pulse width (vpw) bit format digital noise filter collision detection hardware cyclical redundancy check generation and checking two power-saving modes with autom atic wakeup on network activity polling or cpu interrupts block mode receive and transmit 4x receive mode, 41.6 kbps digital loopback mode analog loopback mode in-frame response (ifr) types 0, 1, 2, and 3 note familiarity with the sae standard j1850 class b data communication network interface specification is recommended before proceeding. first-time users of the bdlc should obtain the byte data link controller reference manual, freescale document order number bdlcrm/ad. 15.3 functional description figure 15-1 shows the organization of the bdlc module. the cpu interface contains the software addressable registers and provides the link between the cpu and the buffers. the buffers provide storage for data received and data to be transmitted onto the j1850 bus. the protocol handler is responsible for the encoding and decoding of data bits and special message symbols during trans mission and reception. the mux interface provides the link between the bdlc digital section and the analog physical interface. the wave shaping, driving, and digitizing of data is performed by the physical interface. use of the bdlc module in mess age networking fully implements the sae standard j1850 class b data communication network interface specification.
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 214 freescale semiconductor figure 15-1. bdlc block diagram 15.4 bdlc operating modes the bdlc has five main modes of operation which inte ract with the power supplies, pins, and rest of the mcu as shown in figure 15-2 . figure 15-2. bdlc operating modes state diagram cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc v dd > v dd (minimum) and power off reset bdlc stop run v dd v dd (minimum) stop instruction or from any mode bdlc wait network activity or wait instruction and wcm = 1 wait instruction and wcm = 0 any mcu reset source asserted no mcu reset source asserted any mcu reset source asserted network activity or other mcu wakeup other mcu wakeup (cop, illaddr, pu, reset, lvr, por)
power-conserving modes m68hc12b family data sheet, rev. 9.1 freescale semiconductor 215 15.4.1 power off mode for guaranteed bdlc operation, this mode is entered from reset mode when the bdlc supply voltage, v dd , drops below its minimum specified value. the bdlc is placed in reset mode by low-voltage reset (lvr) before being powered down. in power off mode, the pin input and output specifications are not guaranteed. 15.4.2 reset mode this mode is entered from power off mode when the bdlc supply voltage, v dd , rises above its minimum specified value (v dd ?10%) and an mcu reset source is asserted. the internal mcu reset must be asserted while powering up the bdlc or an unknown state is entered and correct operation cannot be guaranteed. reset mode is also entered from any other mode when any reset source is asserted. in reset mode, the internal bdlc voltage references are operative, v dd is supplied to the internal circuits which are held in their reset state, and the internal bdlc system clock is running. registers assume their reset condition. because outputs are held in their progr ammed reset state, inputs and network activity are ignored. 15.4.3 run mode this mode is entered from reset mode after all mcu reset sources are no longer asserted. run mode is entered from the bdlc wait mode when activity is sensed on the j1850 bus. run mode is entered from the bdlc stop mode when network activity is sensed, although messages are not received properly until the clocks have stabilized and the cpu is also in run mode. in this mode, normal network operation takes place. ensure that all bdlc transmissions have ceased before exiting this mode. 15.5 power-conserving modes the bdlc has three power-conserving modes: 1. bdlc wait and cpu wait mode 2. bdlc stop and cpu wait mode 3. bdlc stop and cpu stop mode depending upon the logic level of the wcm bit in bdlc control register 1 (bcr1), the bdlc enters a power-conserving mode when the cpu executes the stop or wait instruction. when a power-conserving mode is ente red, any activity on the j1850 ne twork causes the bdlc to exit low-power mode. when exiting from bdlc stop mode, the bdlc generates an unmaskable interrupt of the cpu. this wakeup interrupt state is reflect ed in the bdlc state vector register (bsvr) and encoded as the highest priority interrupt. wait mode or stop mode does not reset the bdlc registers upon bdlc wakeup.
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 216 freescale semiconductor to disengage a bdlc node from receiving j1850 traffic: verify all bsvr flags are clear. do not load the bdr. set the aloop bit (after placing the analog tr ansceiver into loopback mode) or dloop bit in bcr2. the bdlc can then be put into wait mode or stop mode and does not wake up with j1850 traffic. depending upon which low-power mode instruction t he cpu executes and which mode the bdlc enters, the message which wakes up the bdlc (and the cpu) may not be received correct ly. three possibilities are described here. these descriptions apply regardless of whether the bdlc is in normal or 4x mode when the stop or wait instruction is executed. 15.5.1 bdlc wait and cpu wait mode this power-saving mode is entered automatically fr om run mode when the wcm bit in bcr1 register is cleared followed by a cpu wait instruction. in bdlc wait mode, the bdlc cannot drive data. a subsequent j1850 network rising edge wakes up the bdlc. in this mode, the bdlc internal clocks continue to run as do the mcu clocks. t he first passive-to-active transition on the j1850 network generates a cpu inte rrupt request by the bdlc which wakes up the bdlc and cpu. the bdlc correctly receives the entire message which generated the cpu interrupt request. note ensure that all transmissions are complete or aborted prior to putting the bdlc into wait mode (wcm = 0 in bcr1). 15.5.2 bdlc stop and cpu wait mode this power-conserving mode is entered automatically from run mode when the wcm bit in the bcr1 register is set followed by a cpu wait instruction. this is the lowest-power mode that the bdlc can enter. in this mode: the bdlc internal clocks are stopped. the cpu internal clocks continue to run. the bdlc awaits j1850 network activity. the first passive-to-active transit ion on the j1850 network generates a non-maskable ($20) cpu interrupt request by the bdlc, allowing the cpu to restart the bdlc internal clocks. to correctly receive future j1850 wakeup traffic, users must read an eof (end of frame) in the bsvr prior to placing the bdlc into stop mode (wcm = 1). then, the new message which wakes up the bdlc from the bdlc stop mode and the cpu from th e cpu wait mode, is received correctly. note ensure that all transmissions are complete or aborted prior to putting the bdlc into stop mode (wcm = 1 in bcr1).
loopback modes m68hc12b family data sheet, rev. 9.1 freescale semiconductor 217 15.5.3 bdlc stop and cpu stop mode this power-conserving mode is entered automatically from run mode when the wcm bit in the bcr1 register is set followed by a cpu stop instruction. this is the lowest-power mode that the bdlc can enter. in this mode: the bdlc internal clocks are stopped. the cpu internal clocks are stopped. the bdlc awaits j1850 network activity. the first passive-to-active transit ion on the j1850 network generates a non-maskable ($20) cpu interrupt request by the bdlc, allowing the cpu clocks to restart and the bdlc internal clocks to restart. therefore, the new message which wakes up the bd lc from the bdlc stop mode and the cpu from the cpu wait mode are not received correctly. this is due primarily to the time required for the mcu?s oscillator to stabilize before the clocks can be applied internally to the other mcu modules, including the bdlc. note ensure that all transmissions are complete or aborted prior to putting the bdlc into stop mode (wcm = 1 in bcr1). 15.6 loopback modes two loopback modes are used to determine the source of bus faults. 15.6.0.1 digital loopback mode when a bus fault has been detected, the digital loopbac k mode is used to determine if the fault condition is caused by failure in the node?s internal circuits or elsewhere in the network, including the node?s analog physical interface. in this mode, the transmit digita l output pin (bdtxd) and the receive digital input pin (bdrxd) of the digital interface are disconnected from the analog physical interface and tied together to allow the digital portion of the bdlc to transmit and receive its own messages without driving the j1850 bus. 15.6.0.2 analog loopback mode analog loopback mode is used to determine if a bus fault has been caused by a failure in the node?s off-chip analog transceiver or elsewhere in the network. the bdlc analog loopback mode does not modify the digital transmit or receive functions of the bdlc. it does, however, ensure that once analog loopback mode is exited, the bdlc waits for an idle bus condition before participation in network communication resumes. if the off-chip analog transce iver has a loopback mode, it usually causes the input to the output drive stage to be looped back into t he receiver, allowing the node to receive messages it has transmitted without driving the j1850 bus. in th is mode, the output to the j1850 bus typically is high impedance. this allows the communication path thr ough the analog transceiver to be tested without interfering with network activity. using the bdlc analog loopback mode in conjunction with the analog transceiver?s loopback mode ensures that, once the off-chip analog transceiver has exited loopback mode, the bdlc does not begin communicating be fore a known condition exists on the j1850 bus.
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 218 freescale semiconductor 15.7 bdlc mux interface the mux (multiplex) interface is responsible for bit encoding/decoding and digital noise filtering between the protocol handler and the physical interface. 15.7.1 rx digital filter the receiver section of the bdlc includes a digital lo w-pass filter to remove narrow noise pulses from the incoming message. an outline of the digital filter is shown in figure 15-3 . figure 15-3. bdlc rx digital filter block diagram 15.7.1.1 operation the clock for the digital filter is provided by the mux interface clock (see f bdlc parameter in table 15-2 ). at each positive edge of the clock signal, the current state of the receiver physical interface (bdrxd) signal is sampled. the bdrxd signal state is used to determine whether the counter should increment or decrement at the next negat ive edge of the clock signal. the counter increments if the input data sample is high but decrements if the input sample is low. therefore, the counter progresses either up toward 15 if, on average, the bdrxd signal remains high or progresses down toward 0 if, on aver age, the bdrxd signal remains low. when the counter eventually reaches the value 15, the digital filter decides that the condition of the bdrxd signal is at a stable logic level 1 and the data latch is set, causing the filtered rx data signal to become a logic level 1. furthermore, the counter is prevented from overflowing and can be decremented only from this state. alternatively, should the counter even tually reach the value 0, the digita l filter decides that the condition of the bdrxd signal is at a stable logic level 0 and t he data latch is reset, causing the filtered rx data signal to become a logic level 0. furthermore, t he counter is prevented from underflowing and can be incremented only from this state. the data latch retains its value until the counter next reaches the opposite end point, signifying a definite transition of the signal. 4-bit up/down counter data latch up/down out filtered rx data out mux input sync dq rx data from physical interface clock (bdrxd) dq interface
bdlc mux interface m68hc12b family data sheet, rev. 9.1 freescale semiconductor 219 15.7.1.2 performance the performance of the digital filter is best descri bed in the time domain rather than the frequency domain. if the signal on the bdrxd signal transitions, there is a delay before that transition appears at the filtered rx data output signal. this delay is between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling points. this f ilter delay must be taken into account when performing message arbitration. for example, if the frequency of the mux interface clock (f bdlc ) is 1.0486 mhz, then the period (t bdlc ) is 954 ns and the maximum filter delay in the absence of noise is 15.259 s. the effect of random noise on the bdrxd signal depends on the characteristics of the noise itself. narrow noise pulses on the bdrxd signal is ignored completely if they are shorter than the filter delay. this provides a degree of low pass filtering. if noise occurs during a symbol transition, the dete ction of that transition can be delayed by an amount equal to the length of the noise burst. this is a refl ection of the uncertainty of where the transition is actually occurring within the noise. noise pulses that are wider than the filter delay, but narrower than the shortest allowable symbol length, are detected by the next stage of the bd lc?s receiver as an invalid symbol. noise pulses that are longer than the shortest allowabl e symbol length are detected normally as an invalid symbol or as invalid data wh en the frame?s crc is checked. 15.7.2 j1850 frame format all messages transmitted on the j1850 bus are structured using the format shown in figure 15-4 . j1850 states that each message has a maximum length of 101 pwm bit times or 12 vpw bytes, excluding sof, eod, nb, and eof, with each byte tr ansmitted most significant bit (msb) first. all vpw symbol lengths in the following descripti ons are typical values at a 10.4-kbps bit rate. 15.7.2.1 sof ? start-of-frame symbol all messages transmitted onto the j1850 bus must begin with a long-active 200 s period sof symbol. this indicates the start of a new message transmi ssion. the sof symbol is not used in the crc calculation. data e o d optional i f s idle sof priority (data0) message id (data1) data n crc n b ifr eof idle figure 15-4. j1850 bus message format (vpw)
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 220 freescale semiconductor 15.7.2.2 data ? in-message data bytes the data bytes contained in the message include the me ssage priority/type, message id byte (typically, the physical address of the responder), and any actual data being transmitted to the receiving node. the message format used by the bdlc is similar to the 3-byte consolidated header message format outlined by the sae j1850 document. see sae j1850 ? class b data comm unications network interface specification for more information about 1- and 3-byte headers. messages transmitted by the bdlc onto the j1850 bus must contai n at least one data byte, and, therefore, can be as short as one data byte and one crc byte. each data byte in the message is eight bits in length and is transmitt ed msb (most significant bit) to lsb (least significant bit). 15.7.2.3 crc ? cyclical redundancy check byte this byte is used by the receiver(s) of each messa ge to determine if any errors have occurred during the transmission of the message. the bdlc calculates the crc byte and appends it onto any messages transmitted onto the j1850 bus. it also performs crc detection on any messages it receives from the j1850 bus. crc generation uses the divisor polynomial x 8 + x 4 + x 3 + x 2 + 1. the remainder polynomial initially is set to all 1s. each byte in the message after the star t-of-frame (sof) symbol is processed serially through the crc generation circuitry. the one?s complement of t he remainder then become s the 8-bit crc byte, which is appended to the message after the data bytes, in msb-to-lsb order. when receiving a message, the bdlc uses the same divisor polynomial. all data bytes, excluding the sof and end-of-data symbols (eod) but including the crc byte, are used to check the crc. if the message is error free, the remainder polynomial equals x 7 + x 6 + x 2 = $c4, regardless of the data contained in the message. if the calc ulated crc does not equal $c4, the bdlc recognizes this as a crc error and sets the crc error flag in the bsvr. 15.7.2.4 eod ? end-of-data symbol the eod symbol is a long 200- s passive period on the j1850 bus used to signify to any recipients of a message that the transmission by the originator has completed. no flag is set upon reception of the eod symbol. 15.7.2.5 ifr ? in-frame response bytes the ifr section of the j1850 message format is optional. users desiring further definition of in-frame response should review the sae j1850 ? class b data communications network interface specification. 15.7.2.6 eof ? end-of-frame symbol this symbol is a long 280- s passive period on the j1850 bus and is longer than an end-of-data (eod) symbol, which signifies the end of a message. since an eof symbol is longer than a 200- s eod symbol, if no response is transmitted afte r an eod symbol, it becomes an eof, and the message is assumed to be completed. the eof flag is set upon receiving the eof symbol. 15.7.2.7 ifs ? interframe separation symbol the ifs symbol is a 20- s passive period on the j1850 bus which allows proper synchronization between nodes during continuous message transmission. the ifs symbol is transmitted by a node after the completion of the end-of-frame (eof) period and, therefore, is seen as a 300- s passive period.
bdlc mux interface m68hc12b family data sheet, rev. 9.1 freescale semiconductor 221 when the last byte of a message has been transmitt ed onto the j1850 bus and the eof symbol time has expired, all nodes then must wait for the ifs symbol ti me to expire before tran smitting a start-of-frame (sof) symbol, marking the beginning of another message. however, if the bdlc is waiting for the ifs period to expire before beginning a transmission and a rising edge is detected before the ifs time has expired, it synchronizes internally to that edge. a rising edge may occur during the ifs period because of varying clock tolerances and loading of the j1850 bus, causing different nodes to observe the completion of the ifs per iod at different times. to allow for individual clock tolerances, receivers must sy nchronize to any sof occurring during an ifs period. 15.7.2.8 break ? break the bdlc cannot transmit a break symbol. if the bdlc is transmitting at the time a break is detec ted, it treats the break as if a transmission error had occurred and halts transmission. if the bdlc detects a break symbol while receiving a message, it treats the break as a reception error and sets the invalid symbol flag in the bsvr, also ignori ng the frame it was receiv ing. if while receiving a message in 4x mode, the bdlc detec ts a break symbol, it treats the break as a reception error, sets the invalid symbol flag, and exits 4x mode (for exampl e, the rx4xe bit in bcr2 is cleared automatically). if bus control is required after the break symbol is received and the ifs time has elapsed, the programmer must resend the transmission byte using highest priority. 15.7.2.9 idle ? idle bus an idle condition exists on the bus during any passi ve period after expiration of the ifs period (for example, > 300 s). any node sensing an idle bus conditi on can begin transmission immediately. 15.7.3 j1850 vpw symbols huntsinger?s variable pulse-width modulation (vpw) is an encoding technique in which each bit is defined by the time between successive tr ansitions and by the level of the bus between transitions (for instance, active or passive). active and passive bits are used alternately. this encoding technique is used to reduce the number of bus transitions for a given bit rate. each logic 1 or logic 0 contains a si ngle transition and can be at either the active or passive level and one of two lengths, either 64 s or 128 s (t nom at 10.4 kbps baud rate), depending upon the encoding of the previous bit. the start-of-frame (sof), end-of-data (eod), end-of-frame (eof), and inter-frame separation (ifs) symbols are always encoded at an assigned level and length. see figure 15-5 . each message begins with an sof symbol, an active sy mbol, and, therefore, each data byte (including the crc byte) begins with a passive bit, regardl ess of whether it is a logic 1 or a logic 0. all vpw bit lengths stated in the descriptions here are typical values at a 10.4-kbps bit rate. eof, eod, ifs, and idle, however, are not driven j1850 bus stat es. they are passive bus periods observed by each node?s cpu.
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 222 freescale semiconductor figure 15-5. j1850 vpw symbols with nominal symbol times 15.7.3.1 logic 0 a logic 0 is defined as: an active-to-passive transition followed by a passive period 64 s in length, or a passive-to-active transition followed by an active period 128 s in length see figure 15-5(a) . 15.7.3.2 logic 1 a logic 1 is defined as: an active-to-passive transition followed by a passive period 128 s in length, or a passive-to-active transition followed by an active period 64 s in length see figure 15-5(b) . 15.7.3.3 normalization bit (nb) the nb symbol has the same property as a logic 1 or a logic 0. it is used only in ifr message responses. 15.7.3.4 break signal (break) the break signal is defined as a passive-to-active tr ansition followed by an active period of at least 240 s (see figure 15-5(c) ). 128 s active passive 64 s or (a) logic 0 128 s active passive 64 s or (b) logic 1 200 s active passive (d) start of frame active passive (f) end of frame 240 s (c) break 200 s (e) end of data 280 s (g) inter-frame 20 s 300 s idle > 300 s (h) idle separation
bdlc mux interface m68hc12b family data sheet, rev. 9.1 freescale semiconductor 223 15.7.3.5 start-of-frame symbol (sof) the sof symbol is defined as passive-to-active transition followed by an active period 200 s in length (see figure 15-5(d) ). this allows the data bytes which follow the sof symbol to begin with a passive bit, regardless of whether it is a logic 1 or a logic 0. 15.7.3.6 end-of-data symbol (eod) the eod symbol is defined as an active-to-passive transition followed by a passive period 200 s in length (see figure 15-5(e) ). 15.7.3.7 end-of-frame symbol (eof) the eof symbol is defined as an active-to-pa ssive transition followed by a passive period 280 s in length (see figure 15-5(f) ). if no ifr byte is transmitted after an eod symbol is transmitted, another 80 s the eod becomes an eof, indicating completion of the message. 15.7.3.8 inter-frame separation symbol (ifs) the ifs symbol is defined as a passive period 300 s in length. the 20- s ifs symbol contains no transition, since when it is used it always appends to a 280- s eof symbol (see figure 15-5(g) ). 15.7.3.9 idle an idle is defined as a passive period greater than 300 s in length. 15.7.4 j1850 vpw valid/inval id bits and symbols the timing tolerances for receiving data bits and symbols from the j1850 bus have been defined to allow for variations in oscillator frequencies. in many case s, the maximum time allowed to define a data bit or symbol is equal to the minimum time allo wed to define another data bit or symbol. since the minimum resolution of the bdlc for deter mining what symbol is bei ng received is equal to a single period of the mux interface clock (t bdlc ), an apparent separation in these maximum time/minimum time concurrences e quals one cycle of t bdlc . this one clock resolution allows the bdlc to different iate properly between the different bits and symbols. this is done without reducing the valid window for rece iving bits and symbols fr om transmitters onto the j1850 bus, which has varyi ng oscillator frequencies. in huntsinger?s variable pulse width (vpw) modulati on bit encoding, the tolerances for both the passive and active data bits received and the symbols receiv ed are defined with no gaps between definitions. for example, the maximum length of a passive logic 0 is equal to the minimum lengt h of a passive logic 1, and the maximum length of an active logic 0 is equa l to the minimum length of a valid sof symbol. see figure 15-6 , figure 15-7 , and figure 15-8 .
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 224 freescale semiconductor figure 15-6. j1850 vpw received passive symbol times 15.7.4.1 invalid passive bit see figure 15-6(1) . if the passive-to-active received transiti on beginning the next data bit or symbol occurs between the active-to-passive transiti on beginning the current data bit (or symbol) and a , the current bit would be invalid. 15.7.4.2 valid passive logic 0 see figure 15-6(2) . if the passive-to-active received transition beginning the next data bit (or symbol) occurs between a and b , the current bit would be considered a logic 0. 15.7.4.3 valid passive logic 1 see figure 15-6(3) . if the passive-to-active received transition beginning the next data bit (or symbol) occurs between b and c , the current bit would be considered a logic 1. 15.7.4.4 valid eod symbol see figure 15-6(4) . if the passive-to-active received transition beginning the next data bit (or symbol) occurs between c and d , the current symbol would be considered a valid end-of-data symbol (eod). a bc b a (1) invalid passive bit (2) valid passive logic 0 (3) valid passive logic 1 64 s 128 s cd (4) valid eod symbol 200 s active passive active passive active passive active passive
bdlc mux interface m68hc12b family data sheet, rev. 9.1 freescale semiconductor 225 figure 15-7. vpw received passive eof and ifs symbol times 15.7.4.5 valid eof and ifs symbols in figure 15-7(1) , if the passive-to-active received transi tion beginning the sof symbol of the next message occurs between a and b , the current symbol is considered a valid end-of-frame (eof) symbol. see figure 15-7(2) . if the passive-to-active received transi tion beginning the sof symbol of the next message occurs between c and d , the current symbol is considered a valid eof symbol followed by a valid inter-frame separation symbol (ifs). all nodes must wait until a valid ifs symbol time has expired before beginning transmission. however, due to vari ations in clock frequencies and bus loading, some nodes may recognize a valid ifs symbol before others and immediately begin transmitting. therefore, any time a node waiting to transmit detects a passi ve-to-active transition once a valid eof has been detected, it should immediately begin transmi ssion, initiating the arbitration process. 15.7.4.6 idle bus in figure 15-7(2) , if the passive-to-active received transition beginning the start-of-frame (sof) symbol of the next message does not occur before d, the bus is considered to be idle, and any node wishing to transmit a message may do so immediately. cd (2) valid eof+ 280 s 300 s a b ( 1) valid eof symbol active passive active passive ifs symbol
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 226 freescale semiconductor figure 15-8. j1850 vpw received active symbol times 15.7.4.7 invalid active bit in figure 15-8(1) , if the active-to-passive received transition b eginning the next data bit (or symbol) occurs between the passive-to-active transition beginning the current data bit (or symbol) and a , the current bit would be invalid. 15.7.4.8 valid active logic 1 in figure 15-8(2) , if the active-to-passive received transition b eginning the next data bit (or symbol) occurs between a and b , the current bit would be considered a logic 1. 15.7.4.9 valid active logic 0 in figure 15-8(3) , if the active-to-passive received transition b eginning the next data bit (or symbol) occurs between b and c , the current bit would be considered a logic 0. 15.7.4.10 valid sof symbol in figure 15-8(4) , if the active-to-passive received transition b eginning the next data bit (or symbol) occurs between c and d , the current symbol would be considered a valid sof symbol. a bc b a (1) invalid active bit (2) valid active logic 1 (3) valid active logic 0 64 s 128 s cd (4) valid sof symbol 200 s active passive active passive active passive active passive
bdlc mux interface m68hc12b family data sheet, rev. 9.1 freescale semiconductor 227 figure 15-9. j1850 vpw received break symbol times 15.7.4.11 valid break symbol in figure 15-9 , if the next active-to-passive received transition does not occur until after e , the current symbol is considered a valid break symbol. a break symbol should be followed by a start-of-frame (sof) symbol beginning the next message to be transmitted onto the j1850 bus. see 15.7.2 j1850 frame format for bdlc response to break symbols. 15.7.5 message arbitration message arbitration on the j1850 bus is accompli shed in a non-destructive manner, allowing the message with the highest priority to be transmitted, wh ile any transmitters which lose arbitration simply stop transmitting and wait for an idle bus to begin transmitting again. if the bdlc wants to transmit onto the j1850 bus, but detects that another message is in progress, it waits until the bus is idle. however, if multiple nodes beg in to transmit in the same synchronization window, message arbitration occurs beginning with the first bi t after the sof symbol and continues with each bit thereafter. if a write to the bdr (for instance, to initiate transmission) occurred on or before 104 t bdlc from the received rising edge, then the bdlc transmits and arbitrates for the bus. if a cpu write to the bdr occurred after 104 t bdlc from the detection of the rising edge, then t he bdlc does not transmit, but waits for the next ifs period to expire before attempting to transmit the byte. the variable pulse-width modulation (vpw) symbols and j1850 bus electrical c haracteristics are chosen carefully so that a logic 0 (active or passive type) al ways dominates over a logic 1 (active or passive type) simultaneously transmitted. hence, logic 0s are said to be dominant and logic 1s are said to be recessive. when a node detects a dominant bit on bdrxd when it transmitted a recessive bit, it loses arbitration and immediately stops transmitting. this is known as bitwis e arbitration (see figure 15-10 ). since a logic 0 dominates a logic 1, the message with the lowest value has the highest priority and always wins arbitration. for instance, a message with priority 000 wins arbitration over a message with priority 011. this method of arbitration works no matter how m any bits of priority encoding are contained in the message. during arbitration, or even throughout the transmi tting message, when an opposite bit is detected, transmission is stopped immediately unl ess it occurs on the eighth bit of a byte. in this case, the bdlc automatically appends up to two extra logic 1 bits and then stops transmitting. these two extra bits are arbitrated normally and thus do not interfere with anot her message. the second logic 1 bit is not sent if (2) valid break symbol 240 s e active passive
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 228 freescale semiconductor the first loses arbitration. if the bdlc has lost arbitration to another valid message, then the two extra logic 1s do not corrupt the current message. however, if the bdlc has lost arbitration due to noise on the bus, then the two extra logic 1s ensure that the current message is detected and ignored as a noise-corrupted message. figure 15-10. j1850 vpw bitwise arbitrations 15.8 bdlc protocol handler the protocol handler is responsib le for framing, arbitration, crc generation/checking, and error detection. the protocol handler conforms to s ae j1850 ? class b data communications network interface. 15.8.1 protocol architecture the protocol handler contains the state machine, rx shadow register, tx shadow register, rx shift register, tx shift register, and loopback multiplexer as shown in figure 15-11 . 15.8.2 rx and tx shift registers the rx shift register gathers received serial data bits from the j1850 bus and makes them available in parallel form to the rx shadow register. the tx shift register takes data, in parallel form, from the tx shadow register and presents it serially to the state machine so that it can be transmitted onto the j1850 bus. 15.8.3 rx and tx shadow registers immediately after the rx shift register has completed shifting in a byte of data, this data is transferred to the rx shadow register and rdrf or rxifr is set (see 15.9.3 bdlc state vector register ). an interrupt is generated if the interrupt enable bit (ie) in bcr1 is set. after the transfer takes place, this new data byte in the rx shadow register is available to the cpu interface, and the rx shift register is ready to shift in the next byte of data. data in the rx shadow register must be retrieved by the cpu before it is overwritten by new data from the rx shift register. transmitter a transmitter b j1850 bus sof data bit 1 data bit 4 data bit 5 0 transmitter a detects an active state on the bus and stops transmitting transmitter b wins passive active passive active passive active 0 0 1 1 1 data bit 2 1 1 1 data bit 3 0 0 0 0 1 arbitration and continues transmitting
bdlc protocol handler m68hc12b family data sheet, rev. 9.1 freescale semiconductor 229 figure 15-11. bdlc protocol handler outline once the tx shift register has completed its shifting o peration for the current byte, the data byte in the tx shadow register is loaded into the tx shift register. a fter this transfer takes place, the tx shadow register is ready to accept new data from the cpu when the tdre flag in the bsvr is set. 15.8.4 digital loopback multiplexer the digital loopback multiplexer connec ts rxd to either bdtxd or bdrxd, depending on the state of the dloop bit in the bcr2. (see 15.9.2 bdlc control register 2 .) 15.8.5 state machine all functions associated with performing the protocol are executed or controlled by the state machine. the state machine is responsible for fr aming, collision detect ion, arbitration, crc generation/che cking, and error detection. these sections describe the bd lc?s actions in a va riety of situations. 15.8.5.1 4x mode the bdlc can exist on the same j1850 bus as modul es which use a special 4x (41.6 kbps) mode of j1850 variable pulse width modulation (vpw) operation. the bdlc cannot transmit in 4x mode, but it can receive messages in 4x mode, if the rx4x bit is set in bcr2. if the rx4x bit is not set in the bcr2, any 4x message on the j1850 bus is treated as noise by the bdlc and is ignored. 15.8.5.2 receiving a message in block mode although not a part of the sae j1850 protocol, the bdlc does allow for a specia l block mode of operation of the receiver. as far as the bdlc is concern ed, a block mode message is simply a long j1850 frame rx shift register to cpu interface and rx/tx buffers state machine to physical interface rx data tx data control 8 tx shift register bdtxd rxd control 8 rx shadow register tx shadow register loopback bdrxd bdtxd multiplexer dloop from bcr2 aloop loopback control
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 230 freescale semiconductor that contains an indefinite number of data bytes. all ot her features of the frame remain the same, including the sof, crc, and eod symbols. another node wishing to send a block mode transmissi on must first inform all other nodes on the network that this is about to happen. this is usually ac complished by sending a special predefined message. 15.8.5.3 transmitting a message in block mode a block mode message is transmitted inherently by simply loading the bytes one by one into the bdr until the message is complete. the programmer should wait until the tdre flag (see 15.9.3 bdlc state vector register ) is set prior to writing a new byte of data into the bdr. the bdlc does not contain any predefined maximum j1850 message length requirement. 15.8.5.4 j1850 bus errors the bdlc detects several types of transmit and rece ive errors which can occur during the transmission of a message onto the j1850 bus. transmission error ? if the message transmitted by the bdlc c ontains invalid bits or framing symbols on non-byte boundaries, this constitutes a transmissi on error. when a transmission error is detected, the bdlc immediately ceases transmitting. the e rror condition is reflected in the bsvr (see table 15-1 ). if the interrupt enable bit (ie in bcr1) is set, a cpu interrupt request from the bdlc is generated. crc error ? a cyclical redundancy check (crc) error is de tected when the data bytes and crc byte of a received message are processed and the crc calculation result is not equal. the crc code detects any single and 2-bit errors, as well as all 8-bit burst errors and almost all other types of errors. the crc error flag (in bsvr) is set when a crc error is detected. (see 15.9.3 bdlc state vector register .) symbol error ? a symbol error is detected when an abnormal (invalid) symbol is detected in a message being received from the j1850 bus. the invalid sy mbol is set when a symbol error is detected. (see 15.9.3 bdlc state vector register .) framing error ? a framing error is detected if an eod or eof symbol is detected on a non-byte boundary from the j1850 bus. a framing error also is detected if the bdlc is transmitting the eod and instead receives an active symbol. t he symbol invalid, or the out-of-range flag, is set when a framing error is detected. (see 15.9.3 bdlc state vector register .) bus fault ? if a bus fault occurs, the response of the bdlc depends upon the type of bus fault. if the bus is shorted to battery, the bd lc waits for the bus to fall to a passive state before it attempts to transmit a message. as long as the short remains, the bdlc never attempts to transmit a message onto the j1850 bus. if the bus is shorted to ground, the bdlc sees an id le bus, begins to transmit the message, and then detects a transmission error (in bsvr), since the short to ground does not allow the bus to be driven to the active (dominant) sof state. the bdlc aborts that transmission and waits for the next cpu command to transmit. in any case, if the bus fault is temporary, as s oon as the fault is cleared, the bdlc resumes normal operation. if the bus fault is permanent, it may resu lt in permanent loss of communication on the j1850 bus. (see 15.9.3 bdlc state vector register .) break ? if a break symbol is received while the bdlc is transmitting or receiving, an invalid symbol (in bsvr) interrupt is generat ed. reading the bsvr (see 15.9.3 bdlc state vector register ) clears this interrupt condition. the bdlc waits for the bus to idle, then waits for a start-of-frame (sof) symbol.
bdlc registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 231 the bdlc cannot transmit a break symbol. it can receive a break symbol onl y from the j1850 bus. 15.8.5.5 summary table 15-1 provides a bus error summary. 15.9 bdlc registers eight registers are available for controlling operati on of the bdlc and for communicating data and status information. a full description of each register is given here. 15.9.1 bdlc cont rol register 1 imsg ? ignore message bit this bit disables the receiver until a new start-of-frame (sof) is detected. the bit is cleared automatically by the re ception of an sof symbol or a break symbol. it then generates interrupt requests and allows changes of the status register to occur. however, these interrupts may still be masked by the interrupt enable (ie) bit. when set, all bdlc interrupt requests are masked (except $20 in bsvr) and the status bits are held in their reset st ate. if this bit is set wh ile the bdlc is receiving a message, the rest of the incoming message is ignored. 1 = disable receiver 0 = enable receiver table 15-1. bdlc j1850 bus error summary error condition bdlc function transmission error for invalid bits or framing symbols on non-byte boundaries, invalid symbol interrupt is generated. bdlc stops transmission. cyclical redundancy check (crc) error crc error interrupt is generated. bdlc waits for eof. invalid symbol: bdlc transmits, but receives invalid bits (noise) the bdlc aborts transmission immediately. invalid symbol interrupt is generated. framing error invalid symbol interrupt is gener ated. bdlc waits for end of frame (eof). bus short to v dd the bdlc does not transmit until the bus is idle. invalid symbol interrupt is generated. eof interrupt also must be seen before another transmission attempt. depending on length of the short, loa flag also may be set. bus short to gnd thermal overload shuts down physical interface. fault condition is seen as invalid symbol flag. eof interrupt must also be seen before another transmission attempt. bdlc receives break symbol invalid symbol interrupt is generated. bdlc waits for the next valid sof. address: $00f8 bit 7654321bit 0 read: imsg clks r1 r0 00 ie wcm write: r r reset:11100000 r = reserved figure 15-12. bdlc control register 1 (bcr1)
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 232 freescale semiconductor clks ? clock select bit for j1850 bus communications to take plac e, the nominal bdlc operating frequency (f bdlc ) must always be 1.048576 mhz or 1 mhz. the clks regist er bit allows the user to select the frequency (1.048576 mhz or 1 mhz) used to au tomatically adjust symbol timing. 1 = binary frequency, 1.048576 mhz 0 = integer frequency, 1 mhz r1 and r0 ? rate select bits these bits determine the amount by which the frequency of the mcu cgmxclk signal is divided to form the mux interface clock (f bdlc ) which defines the basic timing resolution of the mux interface. they may be written only once after reset, after which they become read-only bits. the nominal frequency of f bdlc must always be 1.048576 mhz or 1.0 mhz for j1850 bus communications to take place. hence, the value programmed into these bits is dependent on the chosen mcu system clock frequency per table 15-2 . ie ? interrupt enable bit this bit determines whether the bdlc generates cpu interrupt requests in run mode. it does not clear bsvr interrupts when exiting the bdlc stop or bd lc wait modes. interrupt requests are maintained until all of the interrupt request sources are cl eared by performing the specified actions upon the bdlc?s registers (or an mcu reset sets bsvr bits to $00). interrupts that we re pending at the time that this bit is cleared may be lost. if the programmer does not want to use the interrupt capability of the bdlc, the bdlc state vector register (bsvr) can be polled periodically to determine bdlc states. 1 = enable interrupt requests from bdlc 0 = disable interrupt requests from bdlc wcm ? wait clock mode bit this bit determines the operation of the bdlc during cpu wait mode. 0 = run bdlc internal clocks during cpu wait mode. 1 = stop bdlc internal cl ocks during cpu wait mode. table 15-2. bdlc rate selection f xclk frequency r1 r0 division f bdlc 1.049 mhz 0 0 1 1.049 mhz 2.097 mhz 0 1 2 1.049 mhz 4.194 mhz 1 0 4 1.049 mhz 8.389 mhz 1 1 8 1.049 mhz 1.000 mhz 0 0 1 1.00 mhz 2.000 mhz 0 1 2 1.00 mhz 4.000 mhz 1 0 4 1.00 mhz 8.000 mhz 1 1 8 1.00 mhz
bdlc registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 233 15.9.2 bdlc cont rol register 2 this register controls transmitter operations of the bdlc. aloop ? analog loopback mode bit this bit determines if the j1850 bus is driven by the analog physical interface?s final drive stage. the programmer places the transceiver into loopback m ode first, then sets aloop which resets the bdlc state machine to a known state. when the user clears aloop, to indicate the transceiver has been taken out of loopback mode, the bdlc waits for an eof symbol before attempting to transmit. most transceivers have the aloop feature available. 1 = input to the analog physical interface?s final drive stage is looped back to the bdlc receiver. the j1850 bus is not driven. 0 = bdlc digital circuitry drives an output for th e j1850 bus. after the bit is cleared, the bdlc requires the bus to be idle for a minimum of end-of-frame symbol time (t trv4 ) before message reception or a minimum of inter-frame symbol time (t trv6 ) before message transmission. dloop ? digital loopback mode bit this bit determines the source to which the bdlc internal digital receive input is connected and can be used to isolate bus fault conditions. if a fault condition has been detected on the bus, this control bit allows the programmer to connect the digital trans mit output to the digital receive input. in this configuration, data sent from the transmit buffer is reflected back into the re ceive buffer. if no faults exist in the bdlc, the fault is in the physical in terface block or elsewhere on the j1850 bus. when the dloop bit is set, the bdlc is disengaged from the j1850 bus. therefore, the bdlc does not receive an edge from the j1850 bus whic h would normally cause a bsvr non-maskable wakeup interrupt. 1 = bdrxd is connected to bdtxd. th e bdlc is in digital loopback mode. 0 = bdtxd is not connected to bd rxd. the bdlc is taken out of digital loopback mode and can now drive or receive the j1850 bus normally (giv en aloop is not set). after clearing dloop, the bdlc requires the bus to be idle for a minimum of end-of-frame symbol (t tv4 ) time before allowing reception of a message. the bdlc re quires the bus to be idle for a minimum of inter-frame separator symbol (t tv6 ) time before allowing a message to be transmitted. note the dloop bit is a fault condition aid and should never be altered after the bdr is loaded for transmission. changing dloop during a transmission may cause corrupted data to be transmitted onto the j1850 network. before going into digital loopback mode, the rxpol bit in the bard register must be set so that the receive polarity is not expected to be inverted. address: $00fa bit 7654321bit 0 read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: reset:11000000 figure 15-13. bdlc control register 2 (bcr2)
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 234 freescale semiconductor rx4xe ? receive 4x enable bit this bit determines if the bdlc operates at norma l transmit and receive speed (10.4 kbps) or receive only at 41.6 kbps. this feature is useful for fa st downloading data into a j1850 node for diagnostic or factory programming. 1 = bdlc is put in 4x receive-only operation. 0 = bdlc transmits and receives at 10.4 kbps. reception of a break symb ol automatically clears this bit and sets bdlc state vector register (bsvr) to $001c. nbfs ? normalization bit format select bit this bit controls the format of the normalization bit (nb). (see figure 15-14 .) sae j1850 encourages using an active long (logic 0) for in-frame re sponses containing cyclical redundancy check (crc) and an active short (logic 1) for in-frame responses without crc. 0 = nb that is received or transmitted is a 1 wh en the response part of an in-frame response (ifr) ends with a crc byte. nb that is received or transmitted is a 0 when the response part of an in-frame response (ifr) does not end with a crc byte. 1 = nb that is received or transmitted is a 0 wh en the response part of an in-frame response (ifr) ends with a crc byte. nb that is received or transmitted is a 1 when the response part of an in-frame response (ifr) does not end with a crc byte. teod ? transmit end of data bit this bit is set by the programmer to indicate the end of a message is being sent by the bdlc. it appends an 8-bit crc after completing tr ansmission of the current byte . this bit also is used to end an in-frame response (ifr). if the transmit shadow register is full when teod is set, the crc byte is transmitted after the current byte in the tx shift register and the byte in the tx shadow register have been transmitted. (see 15.8.3 rx and tx shadow registers for a description of the transmit shadow register.) once teod is set, the transmit data register empty flag (tdre) in the bdlc state vector register (bsvr) is cleared to allow lo wer priority interrupt s to occur. (see 15.9.3 bdlc state vector register .) 1 = transmit end-of-data (eod) symbol 0 = teod bit is cleared automatically at the rising edge of the first crc bit that is sent or if an error is detected. when teod is used to end an ifr transmission, teod is cleared when the bdlc receives back a valid eod symbol or an error condition occurs. tsifr, tmifr1, tmifr0 ? transmit in-frame response bits these bits control the type of in-frame response being sent. only one of these bits should be set at a time. if more than one are set, the priority encoding l ogic forces the bits to a known value as shown in table 15-3 . for example, if 011 is written to tsifr, tmifr1, and tmifr0, then internally they are encoded as 010. however, when these bits are read back, they read 011. table 15-3. transmit in-frame response bit encoding write/read (1) 1. shaded cells indicate bits which do not af fect internal interpretation. these bits read back as written. internal interpretation tsifr tmifr1 tmifr0 tsifr tmifr1 tmifr0 00 000 0 1 10 0 01 01 0 00 100 1
bdlc registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 235 figure 15-14. types of in-frame response the bdlc supports the in-frame response (ifr) features of j1850. the four types of j1850 ifr are shown in figure 15-14 . the purpose of the in-frame response modes is to allow multiple nodes to acknowledge receipt of the data by responding with their personal id or physical address in a concatenated manner after they have seen the eod symbol. if transmi ssion arbitration is lost by a node while sending its response, it continues to transmit its id/addres s until observing its unique byte in the response stream. for vpw modulation, the first bit of the ifr is always passi ve; therefore, an active normalization bit must be generated by the responder and sent prior to its id/address byte. when there are multiple responders on the j1850 bus, only one normalization bit is sent which assists all other tr ansmitting nodes to sync their responses. tsifr ? transmit single byte ifr with no crc bit (type 1 and type 2) the tsifr bit is used to request the bdlc to transmit the byte in the bdlc data register (bdr) as a single byte ifr with no crc. typically, the byte transmitted is a unique identifier or address of the transmitting (responding) node. see figure 15-14 . 1 = if this bit is set prior to a valid eod being received with no crc error, once the eod symbol has been received the bdlc attempts to transmit the appropriate normalization bit followed by the byte in the bdr. 0 = tsifr bit is cleared automatically, once the bd lc has successfully transmitted the byte in the bdr onto the bus, or teod is set, or an error is detected on the bus. if the programmer attempts to set the tsifr bit immediately after the eod symbol has been received from the bus, the tsifr bit remains in the reset state and no attempt is made to transmit the ifr byte. if a loss of arbitration occurs when the bdlc attempts to transmit and after the ifr byte winning arbitration completes transmission, the bdlc again attempts to transmit the bdr (with no normalization bit). the bdlc continues transmission attempts until an error is detected on the bus, or teod is set, or the bdlc transmission is successful. if loss of arbitration occurs in the last bit of the ifr byte, two additional 1 bits are not sent out because the bdlc attempts to retransmit the byte in the transmit shift register after the irf byte winning arbitration completes transmission. nb data field header crc data field data field data field header header header sof crc crc crc ifr data field eod crc sof sof sof eof eod eod eod eod eof nb id1 idn eod eof nb id type 0 ? no ifr type 1 ? single byte from a single responder type 2 ? single byte from multiple responders type 3 ? multiple bytes from a single responder eod eof
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 236 freescale semiconductor tmifr0 ? transmit multiple byte ifr without crc (type 3) the tmifr0 bit is used to request the bdlc to trans mit the byte in the bdlc data register (bdr) as the first byte of a multiple byte ifr without crc. response ifr bytes are still subject to j1850 message length maximums (see 15.7.2 j1850 frame format and figure 15-14 ). 1 = if set prior to a valid eod being receiv ed with no crc error, once the eod symbol has been received, the bdlc attempts to transmit the appropriate normalization bit followed by ifr bytes. the programmer should set teod after the last ifr byte has been written into the bdr. after teod has been set, the last ifr byte to be transmitted is the last byte which was written into the bdr. 0 = bit is cleared automatically once the bdlc has successfully transmitted the eod symbol, by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the bdr after the tdre interrupt. if the tmifr0 bit is set, the bdlc attempts to transmit the normaliza tion symbol followed by the byte in the bdr. after the byte in the bdr has been loaded into the transmit shift register, a tdre interrupt (see 15.9.3 bdlc state vector register ) occurs similar to the main message transmit sequence. the programmer should then load the next byte of t he ifr into the bdr for transmission. when the last byte of the ifr has been loaded into the bdr, the programmer should set the teod bit in the bcr2. this instructs the bdlc to transmit an eod symbol once the byte in the bdr is transmitted, indicating the end of the ifr portion of the message fram e. the bdlc does not append a crc when the tmifr0 is set. if the programmer attempts to set the tmifr0 bit after the eod symbol has been received from the bus, the tmifr0 bit remains in the reset state, and no attempt is made to transmit an ifr byte. if a loss of arbitration occurs when the bdlc is tr ansmitting, the tmifr0 bit is cleared, and no attempt is made to retransmit the byte in the bdr. if loss of arbitration occurs in the last bit of the ifr byte, two additional 1 bits are sent out. note the extra logic 1 bits are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise onto the j1850 bus from a corrupted message. tmifr1 ? transmit multiple byte ifr with crc bit (type 3) the tmifr1 bit requests the bdlc to transmit the byte in the bdlc data register (bdr) as the first byte of a multiple byte ifr with crc or as a sing le byte ifr with crc. response ifr bytes are still subject to j1850 message length maximums (see 15.7.2 j1850 frame format and figure 15-14 ). 1 = if this bit is set prior to a valid eod being received with no crc error, once the eod symbol has been received, the bdlc attempts to transmit the appropriate normalization bit followed by ifr bytes. the programmer should set teod after the last ifr byte has been written into the bdr. after teod has been set and the last ifr byte has been transmitted, the crc byte is transmitted. 0 = the bit is cleared automatically, once the bd lc has successfully tr ansmitted the crc byte and eod symbol, by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the bdr after the tdre interrupt.
bdlc registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 237 if the tmifr1 bit is set, the bdlc attempts to transmit the normaliza tion symbol followed by the byte in the bdr. after the byte in the bdr has been loaded into the transmit shift register, a tdre interrupt (see 15.9.3 bdlc state vector register ) occurs similar to the main message transmit sequence. the programmer should then load the next byte of t he ifr into the bdr for transmission. when the last byte of the ifr has been loaded into the bdr, the programmer should set the teod bit in the bdlc control register 2 (bcr2). this instructs the bdlc to transmit a crc byte once the byte in the bdr is transmitted, and then transmit an eod symbol, indi cating the end of the ifr portion of the message frame. however, to transmit a single byte followed by a crc byte, the programmer s hould load the byte into the bdr before the eod symbol has been received, and then set the tmifr1 bit. once the tdre interrupt occurs, the programmer sets the teod bit in the bcr2. this results in the byte in the bdr being the only byte transmitted before the if r crc byte, and no tdre interrupt is generated. if the programmer attempts to set the tmifr1 bit immediately after the eod symbol has been received from the bus, the tmifr1 bit remains in the reset state, and no attempt is made to transmit an ifr byte. if a loss of arbitration occurs when the bdlc is trans mitting any byte of a multiple byte ifr, the bdlc goes to the loss of arbitration state, sets the appropriate flag, and ceases transmission. if the bdlc loses arbitration during the ifr, the tmifr1 bit is cleared and no attempt is made to retransmit the byte in the bdr. if loss of arbitration occurs in the last bit of the ifr byte, two additional 1 bits are sent out. note the extra logic 1 bits are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise on the j1850 bus from corrupting a message. 15.9.3 bdlc state vector register this register is provided to substantially decreas e the cpu overhead associated with servicing interrupts while under operation of a multiplex protocol. it provides an index offset that is directly related to the bdlc?s current state, which can be used with a us er-supplied jump table to rapidly enter an interrupt service routine. this eliminates the need for the us er to maintain a duplicate state machine in software. i0, i1, i2, i3 ? interrupt source bits these bits indicate the source of the pending interrupt request. bits are encoded according to table 15-4 . address: $00f9 bit 7654321bit 0 read: 0 0 i3 i2 i1 i0 0 0 write: reset:00000000 = unimplemented figure 15-15. bdlc state vector register (bsvr)
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 238 freescale semiconductor bits i0, i1, i2, and i3 are cleared by a read of the bsvr register except when the bdlc data register needs servicing (rdrf, rxifr, or tdre conditions ). rxifr and rdrf can only be cleared by a read of the bsvr register followed by a read of bdr. t dre can either be cleared by a read of the bsvr register followed by a write to the bdlc bdr regist er, or by setting the teod bit in bcr2. clearing an invalid symbol flag requires an eof flag to be re ceived before the bdlc can receive or transmit. if aloop or dloop in bcr2 is set, the bdlc node is disengaged from the j1850 bus. therefore, the bdlc does not receive any data from the j 1850 bus which normally generates bsvr flags. upon receiving a bdlc interrupt, the user may read the value within the bsvr, transferring it to the cpu?s index register. the value can be used to index a jump table to access a service routine. for example: service ldx bsvr fetch state vector number jmp jmptab,xenter service routine, * (must end in an rti) * jmptab jmp serve0service condition #0 nop jmp serve1service condition #1 nop jmp serve2service condition #2 nop . . . jmp serve8service condition #8 end note nop instructions are used only to al ign the jmp instructions onto 4-byte boundaries so that the value in the bsvr can be used intact. each of the service routines must end with an rti instruction to guarantee correct continued operation of the device. the first entry can be omitted since it does not correspond to an interrupt. table 15-4. interrupt sources bsvr i3 i2 i1 i0 interrupt source priority $00 0 0 0 0 no interrupts pending 0 (lowest) $04 0001 received eof 1 $08 0 0 1 0 received ifr byte (rxifr) 2 $0c 0 0 1 1 bdlc rx data register full (rdrf) 3 $10 0 1 0 0 bdlc tx data register empty (tdre) 4 $14 0 1 0 1 loss of arbitration 5 $18 0 1 1 0 cyclical redundancy check (crc) error 6 $1c 0 1 1 1 symbol invalid or out of range 7 $20 1 0 0 0 wakeup 8 (highest)
bdlc registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 239 the service routines should clear all of the source s that are causing the p ending interrupts. clearing a high priority interrupt may still leave a lower priority interrupt pending, in which case bits i0, i1, and i2 of the bsvr reflect the source of the remaining interrupt request. if fewer states are used or if a different software app roach is taken, the jump table can be made smaller or omitted altogether. 15.9.4 bdlc data register this register is used to pass the data to be transmitted to the j1850 bus from the cpu to the bdlc. it is also used to pass data received from the j1850 bus to the cpu. each data byte (after the first one) should be written only after a tx data register empty (tdre) state is indicated in the bsvr. data read from this register is the last data byte received from the j1850 bus. this received data should only be read after an rx data register full (rdrf) interrupt has occurred. (see 15.9.3 bdlc state vector register .) the bdr is double buffered via a transmit shadow regi ster and a receive shadow register. after the byte in the transmit shift register has been transmitted, the byte currently stored in the transmit shadow register is loaded into the transmit shift register. once the trans mit shift register has shifted the first bit out, the tdre flag is set, and the shadow register is ready to accept the next data byte. the receive shadow register works similarly. once a complete byte has been received, the receive shift register stores the newly received byte into the receive shadow register. the rdrf flag is set to indicate that a new byte of data has been received. the programmer has one bdlc byte reception time to read the shadow register and clear the rdrf flag before the shadow regist er is overwritten by the newly received byte. to abort an in-progress transmission, the programmer should stop loading data into the bdr. this causes a transmitter underrun error and the bdlc automatically disables the transmitter on the next non-byte boundary. this means that the earliest a transmission can be halted is after at least one byte plus two extra logic 1 bits have been transmitted. the receiver picks this up as an error and relays it in the state vector register as an invalid symbol error. note the extra logic 1 bits are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise on the j1850 bus from corrupting a message. address: $00fb bit 7654321bit 0 read: bd7 bd6 bd5 bd4 bd3 bd2 bd1 bd0 write: reset: indeterminate after reset figure 15-16. bdlc data register (bdr)
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 240 freescale semiconductor 15.9.5 bdlc analog r oundtrip delay register read: anytime write: once in normal modes or anytime in special mode bard programs the bdlc to compensate for various delays of external transceivers. ate ? analog transceiver enable bit the ate bit is used to select either the on-board or an off-chip analog transceiver. 0 = select off-chip analog transceiver. 1 = select on-board analog transceiver. note this device does not contain an on-board transceiver; ate should be cleared for proper operation. rxpol ? receive pin polarity bit this bit selects the polarity of an incoming signal on the receive pin. some external analog transceivers invert the receive signal from the j1850 bus before feeding it back to the digital receive pin. 0 = select inverted polarity, where exter nal transceiver inverts the receive signal. 1 = select normal/true polarity; true non-inverted si gnal from j1850 bus, for example, the external transceiver does not invert the receive signal. bo3?bo0 ? bard offset bits these bits are used to compensate for the analog transceiver roundtrip delay. table 15-5 shows the expected transceiver delay with respect to bard offset values. address: $00fc bit 7654321bit 0 read: ate rxpol 00 bo3 bo2 bo1 bo0 write: reset:11000111 = unimplemented figure 15-17. bdlc analog roundtrip delay register (bard)
bdlc registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 241 15.9.6 port dlc control register read: anytime write: anytime the bdlc port dlc functions as a general-purpose i/o port. bdlc functions takes precedence over the general-purpose port when enabled. bdlcen ? bdlc enable bit 1 = configure i/o pins for bdlc function. bdlc is active. 0 = configure bdlc i/o pins as g eneral-purpose i/o. bdlc is off. pupdlc ? bdlc pullup enable bit 1 = connects internal pull ups to portdlc i/o pins 0 = disconnects internal pullu ps from portdlc i/o pins rdpdlc ? bdlc reduced drive bit 1 = configure portdlc i/o pins for reduced drive strength. 0 = configure portdlc i/o pins for normal drive strength. table 15-5. offset bit values and transceiver delay bo3?bo0 expected delay ( s) 0000 9 0001 10 0010 11 0011 12 0100 13 0101 14 0110 15 0111 16 1000 17 1001 18 1010 19 1011 20 1100 21 1101 22 1110 23 1111 24 address: $00fd bit 7654321bit 0 read: 0 0 0 0 0 bdlcen pupdlc rdpdlc write: reset:00000000 = unimplemented figure 15-18. port dlc control register (dlcscr)
byte data link co mmunications (bdlc) m68hc12b family data sheet, rev. 9.1 242 freescale semiconductor 15.9.7 port dlc data register read: anytime write: anytime this register holds data to be driven out on port dlc pins or data received from port dlc pins. when configured as an input, a read returns the pin level. when configured as output, a read returns the latched output data. writes do not change pin state when the pins are configured for bdlc output. upon reset, pins are configured for general-purpose high impedance inputs. 15.9.8 port dlc data direction register read: anytime write: anytime dddlc6?dddlc0 ? data direction port dlc bits 1 = configure i/o pin for output 0 = configure i/o pin for input only address: $00fe bit 7654321bit 0 read: 0 bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:0uuuuuuu alternate pin function: dlctx dlcrx = unimplemented u = unaffected figure 15-19. port dlc data register (portdlc) address: $00ff bit 7654321bit 0 read: 0 dddlc6 dddlc5 dddlc4 dddlc3 dddlc2 dddlc1 dddlc0 write: reset:00000000 = unimplemented figure 15-20. port dlc data direction register (ddrdlc)
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 243 chapter 16 mscan12 controller 16.1 introduction the mscan12 is the specific implementation of t he mscan concept targeted for the freescale m68hc12 family of microcontrollers (mcu). the module is a communication controller implement ing the can 2.0 a/b protocol as defined in the specification from robert bosch gmbh dated september 1991. the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field such as: real-time processing reliable operation in the electromagnetic in terference (emi) environment of a vehicle cost effectiveness required bandwidth the mscan12 simplifies the application software by utilizing an advanced buffer arrangement resulting in a predictable real-time behavior. 16.2 external pins the mscan12 uses two external pins, one input (rxcan), and one output (txcan). the txcan output pin represents the logic level on the can: 0 is fo r a dominant state, and 1 is for a recessive state. rxcan is on bit 0 of port can, and txcan is on bit 1. the remaining six pins of port can are controlled by registers in the mscan12 address space. see 16.12.14 mscan12 port can control register and 16.12.16 mscan12 port can data direction register . a typical can system with mscan12 is shown in figure 16-1 . each can station is connected physically to th e can bus lines through a transceiver chip. the transceiver is capable of driving the large current needed for the can and has current protection against defected can or defected stations. 16.3 message storage mscan12 facilitates a sophisticated message stor age system which addresses the requirements of a broad range of network applications.
mscan12 controller m68hc12b family data sheet, rev. 9.1 244 freescale semiconductor figure 16-1. typical can system with mscan12 16.3.1 background modern application layer software is built on two fundamental assumptions: 1. any can node is able to send out a stream of scheduled messages without releasing the bus between two messages. such nodes will arbitrate for the bus right after sending the previous message and will only release the bu s in case of lost arbitration. 2. the internal message queue within any can node is organized so that the highest priority message will be sent out first if more than one message is ready to be sent. this behavior cannot be achieved with a single transmit buffer. that buffer must be reloaded right after the previous message has been sent. this loading proc ess lasts a definite amount of time and has to be completed within the inter-frame sequence (ifs) to be able to send an uninterrupted stream of messages. even if this is feasible for limited can bus speeds, it requires that the central processor unit (cpu) reacts with short latencies to the transmit interrupt. a double buffer scheme would decouple the reloading of the transmit buffers from the actual message being sent and as such reduces the reaction requirements on the cpu. problems may arise if the sending of a message would be finished just while the cpu rel oads the second buffer. in that case, no buffer would then be ready for transmission and the bus would be released. at least three transmit buffers are required to meet the first requirement under all circumstances. the mscan12 has three transmit buffers. the second requirement calls for some sort of inte rnal priorization which the mscan12 implements with the ?local priority? concept described here. can mscan12 can station 1 can station 2 can station n txcan rxcan can system transceiver . . . controller
message storage m68hc12b family data sheet, rev. 9.1 freescale semiconductor 245 16.3.2 receive structures the received messages are stored in a 2-stage first-in /first-out (fifo) input. the two message buffers are mapped into a single memory area (see figure 16-2 ). while the background receive buffer (rxbg) is exclusively associated to the mscan12, the for eground receive buffer (rxfg) is addressable by the cpu12. this scheme simplifies the handler softwa re since only one address area is applicable for the receive process. figure 16-2. user model for message buffer organization both buffers have 13 bytes for storing the can contro l bits, the identifier (standard or extended), and the data contents. for details, see 16.11 programmer?s model of message storage . the receiver full flag (rxf) in the mscan12 receiv er flag register (crflg) signals the status of the foreground receive buffer. when the buffer contains a correctly received message with matching identifier, this flag is set. see 16.12.5 mscan12 receiver flag register . on reception, each message is checked to see if it passes the filter (for details see 16.4 identifier acceptance filter ) and in parallel is written into rxbg. the mscan12 copies the content of rxbg into rxfg (1) , sets the rxf flag, and emits a receive interrupt to the cpu (2) . the user?s receive handler has to read the received message from rxfg and then reset the rxf flag to acknowledge the interrupt and rxfg rxbg tx0 txe prio txe prio txe prio mscan12 cpu bus rxf tx1 tx2
mscan12 controller m68hc12b family data sheet, rev. 9.1 246 freescale semiconductor to release the foreground buffer. a new message, which can follow immediately after the ifs field of the can frame, is received into rxbg. the over-w riting of the background buffer is independent of the identifier filter function. when the mscan12 module is trans mitting, the mscan12 receives its own messages into the background receive buffer, rxbg, but does not overwrite rxfg, generate a receive interrupt, or acknowledge its own messages on the can bus. the ex ception to this rule is in loop-back mode (see 16.12.2 mscan12 module control register 1 ) where the mscan12 treats its own messages exactly like all other incoming messages. the mscan12 receives its own transmitted messages in the event that it loses arbitration. if arbitration is lost, the mscan12 must be prepared to become the receiver. an overrun condition occurs when both the for eground and the background receive message buffers are filled with correctly received messages with acc epted identifiers and another message is correctly received from the bus with an accepted identifier. t he latter message is discarded and an error interrupt with overrun indication is generated if enabled. the msca n12 is still able to transmit messages with both receive message buffers filled, but all incoming messages are discarded. 16.3.3 transmit structures the mscan12 has a triple transmit buffer scheme to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. the three buffers are arranged as shown in figure 16-2 . all three buffers have a 13-byte data structure si milar to the outline of the receive buffers (see 16.11 programmer?s model of message storage ). an additional transmit buffer pr iority register (tbpr) contains an 8-bit local priority field (prio). see 16.11.5 transmit buffer priority register . to transmit a message, the cpu12 has to identify an av ailable transmit buffer which is indicated by a set transmit buffer empty (txe) flag in the mscan12 transmitter flag register (ctflg). see 16.12.7 mscan12 transmitter flag register . the cpu12 then stores the identifier, the control bits, and the data content into one of the transmit buffers. finally, the buffer has to be flagged ready for transmission by clearing the txe flag. the mscan12 then will schedule the message for transmission and will si gnal the successful transmission of the buffer by setting the txe flag. a transmit interrupt will be emitted (1) when txe is set, and this can be used to drive the application software to reload the buffer. if more than one buffer is scheduled for transmission when the can bus becomes available for arbitration, the mscan12 uses the local priority setting of the th ree buffers for prioritizing. for this purpose, every transmit buffer has an 8-bit local priority field (pri o). the application software sets this field when the message is set up. the local priority reflects the priority of this particular message relative to the set of messages being emitted from this node . the lowest binary value of the prio field is defined to be the highest priority. the internal scheduling process takes place whenever the mscan12 arbitrates for the bus. this is also the case after the occurrence of a transmission error. 1. only if the rxf flag is not set 2. the receive interrupt will occur only if not masked. a polling scheme can be applied on rxf also. 1. the transmit interrupt is generated only if no t masked. a polling scheme can be applied on txe also.
identifier acceptance filter m68hc12b family data sheet, rev. 9.1 freescale semiconductor 247 when a high priority message is scheduled by the appl ication software, it may become necessary to abort a lower priority message being set up in one of the three transmit buffers. because messages that are already under transmission cannot be aborted, the user has to request the abort by setting the corresponding abort request flag (abtrq) in the trans mission control register (ctcr). the mscan12 grants the request, if possible, by setting th e corresponding abort request acknowledge (abtak) and the txe flag to release the buffer and by generating a tr ansmit interrupt. the transmit interrupt handler software can tell from the setting of the abtak flag whether the message was aborted (abtak = 1) or sent in the meantime (abtak = 0). 16.4 identifier acceptance filter the identifier acceptance registers (cidar0?ciada r7) define the acceptable patterns of the standard or extended identifier (id10?id0 or id28?id0). any of these bits can be marked don?t care in the identifier mask registers (cidmr0?cidmr7). a filter hit is indicated to the application software by: a set rxf (receive buffer full flag) see 16.12.5 mscan12 receiver flag register ) and three bits in the identifier acceptance control register see 16.12.9 mscan12 identifier acceptance control register ). these identifier hit flags (idhit2?idhit0) clearly ident ify the filter section that caused the acceptance. they simplify the application software?s task to identi fy the cause of the receiver interrupt. when more than one hit occurs (two or more filt ers match), the lower hit has priority. a flexible, programmable generic identifier acceptanc e filter has been introduced to reduce the cpu interrupt loading. the filter is programmable to operate in four different modes: 1. two identifier acceptance filters, each to be applied to the full 29 bits of the identifier and to three bits of the can frame: rtr, ide, and srr. this mode implements two filters for a full length can 2.0b compliant extended identifier. figure 16-3 shows how the first 32-bit filter bank (cidar0?cidar3, cidmr0?cidmr3) produces a filter 0 hit. similarly, the second filter bank (cidar4?cuidar7, cidmr4?cidmr7) produces a filter 1 hit. figure 16-3. 32-bit maskable identifier acceptance filter cidmr2 id28 id21 id20 id15 id14 id7 id6 rtr id10 id3 id2 ide ac7 idr0 idr0 idr1 idr1 idr2 idr3 ac0 ac7 ac0 ac7 ac7 ac0 ac0 ac7 ac0 ac7 ac0 ac7 ac0 ac7 ac0 cidmro cidmr1 cidmr3 cidar3 cidar2 cidar1 cidaro id accepted (filter 0 hit)
mscan12 controller m68hc12b family data sheet, rev. 9.1 248 freescale semiconductor 2. four identifier acceptance filters, each to be applied to: a. 11 bits of the identifier and the rtr bit of can 2.0a messages, or b. 14 most significant bits of the identifier of can 2.0b messages figure 16-4 shows how the first 32-bit filter bank (c idar0?cidar3, cidmr0?cidmr3) produces filter 0 and 1 hit. similarly, the second fi lter bank (cidar4?cuidar7, cidmr4?cidmr7) produces filter 2 and three hits. figure 16-4. 16-bit maskable acceptance filters 3. eight identifier acceptance filters, each to be appli ed to the first eight bits of the identifier. this mode implements eight independent filters for the firs t eight bits of a can 2.0a compliant standard identifier or of a can 2.0b compliant extended identifier. figure 16-5 shows how the first 32-bit filter bank (cidar0?cidar3, cidmr0?cidmr3) produces fi lter 0 to three hits. similarly, the second filter bank (cidar4?cuidar7, cidmr4?cid mr7) produces filter 4 to seven hits. 4. closed filter. no can message will be copied into the foreground buffer rxfg, and the rxf flag will never be set. id28 id21 id20 id15 id14 id7 id6 rtr id10 id3 id2 ide ac7 idr0 idr0 idr1 idr1 idr2 idr3 ac0 ac7 ac0 ac7 ac0 ac7 ac0 cidmro cidmr1 cidar1 cidaro id accepted (filter 0 hit) id accepted (filter 1 hit) ac7 ac0 ac7 ac0 ac7 ac0 ac7 ac0 cidmr2 cidmr3 cidar3 cidar2
identifier acceptance filter m68hc12b family data sheet, rev. 9.1 freescale semiconductor 249 figure 16-5. 8-bit maskable acceptance filters id28 id21 id20 id15 id14 id7 id6 rtr id10 id3 id2 ide ac7 idr0 idr0 idr1 idr1 idr2 idr3 ac0 ac7 ac0 cidmro cidaro id accepted (filter 0 hit) ac7 ac0 ac7 ac0 cidmr1 cidar1 ac7 ac0 ac7 ac0 cidmr2 cidar2 id accepted (filter 1 hit) id accepted (filter 2 hit) ac7 ac0 ac7 ac0 cidmr3 cidar3
mscan12 controller m68hc12b family data sheet, rev. 9.1 250 freescale semiconductor 16.5 interrupts the mscan12 supports four interrupt vectors mapped onto 11 different interrupt sources, any of which can be individually masked. for details, see 16.12.5 mscan12 receiver flag register to 16.12.8 mscan12 transmitter control register . 1. transmit interrupt: at least one of the three transmit buffe rs is empty (not scheduled) and can be loaded to schedule a message for transmission. the empty message buffers txe flags are set. 2. receive interrupt: a message has been successfully received and loaded into the foreground receive buffer. this interrupt will be emitted im mediately after receiving the end of frame (eof) symbol. the rxf flag is set. 3. wakeup interrupt: an activity on the can bus occurr ed during mscan12 internal sleep mode. 4. error interrupt: an overrun, error, or warning condition occurred. the receiver flag register (crflg) will indicate one of these conditions: ? overrun: an overrun condition as described in 16.3.2 receive structures has occurred. ? receiver warning: the receive error counter has reached the cpu warning limit of 96. ? transmitter warning: the transmit error counter has reached the cpu warning limit of 96. ? receiver error passive: the receive error counter has exc eeded the error passive limit of 127 and mscan12 has gone to error passive state. ? transmitter error passive: the transmit error counter has exceeded the error passive limit of 127 and mscan12 has gone to error passive state. ? bus off: the transmit error counter has exceeded 2 55 and mscan12 has gone to bus-off state. 16.5.1 interrupt acknowledge interrupts are associated directly with one or more st atus flags in either the mscan12 receiver flag register (crflg) or the mscan12 transmitter control register (ctcr). interrupts are pending as long as one of the corresponding flags is set. the flags in th e aforementioned registers must be reset within the interrupt handler to handshake the interrupt. the flags are reset through writing a 1 to the corresponding bit position. a flag cannot be cleared if the respective condi tion still prevails. note bit manipulation instructions (bset) must not be used to clear interrupt flags. 16.5.2 interrupt vectors the mscan12 supports four interrupt vectors as shown in table 16-1 . the vector addresses are dependent on the chip integration and to be defined. the relative interrupt priority is also integration dependent and to be defined.
protocol violation protection m68hc12b family data sheet, rev. 9.1 freescale semiconductor 251 16.6 protocol violation protection the mscan12 will protect the user from accidentally violating the can protocol through programming errors. the protection logic implements these features: the receive and transmit error counters ca nnot be written or otherwise manipulated. all registers which control the configuratio n of the mscan12 cannot be modified while the mscan12 is online. the s ftres bit in cmcr0 (see 16.12.1 mscan12 module control register 0 ) serves as a lock to protect these registers: ? mscan12 module control register 1 (cmcr1) ? mscan12 bus timing register 0 and 1 (cbtr0 and cbtr1) ? mscan12 identifier acceptance control register (cidac) ? mscan12 identifier acceptance registers (cidar0?cidar7) ? mscan12 identifier mask registers (cidmr0?cidmr7) the txcan pin is forced to recessive if the cpu goes into stop mode. 16.7 low-power modes in addition to normal mode, the mscan12 has thr ee modes with reduced power consumption compared to normal mode. in sleep and soft-reset mode, power consumption is reduced by stopping all clocks except those to access the registers. in powe r-down mode, all clocks are stopped and no power is consumed. the wait-for-interrupt (wai) and stop instructions put the mcu in low power-consumption standby modes. table 16-2 summarizes the combinations of mscan 12 and cpu modes. a particular combination of modes is entered for the given settings of the bits cswai, slpak, and sftres. for all modes, an mscan wakeup interrupt can occur only if slpak = wupie = 1. while the cpu is in wait mode, the mscan12 can be operated in normal mode and emit interrupts. (registers can be accessed via background debug mode.) table 16-1. mscan12 interrupt vectors function source local mask global mask wakeup wupif wupie i bit error interrupts rwrnif rwrnie twrnif twrnie rerrif rerrie terrif terrie boffif boffie ovrif ovrie receive rxf rxfie transmit txe0 txeie0 txe1 txeie1 txe2 txeie2
mscan12 controller m68hc12b family data sheet, rev. 9.1 252 freescale semiconductor 16.7.1 mscan12 sleep mode the cpu can request the mscan12 to enter this lo w-power mode by asserting the slprq bit in the module configuration register. see figure 16-6 . figure 16-6. sleep request/acknowledge cycle table 16-2. mscan12 versus cpu operating modes mscan mode cpu mode stop wait run power-down cswai = x (1) slpak = x sftres = x 1. x means don?t care. cswai = 1 slpak = x sftres = x sleep cswai = 0 slpak = 1 sftres = 0 cswai = x slpak = 1 sftres = 0 soft reset cswai = 0 slpak = 0 sftres = 1 cswai = x slpak = 0 sftres = 1 normal cswai = 0 slpak = 0 sftres = 0 cswai = x slpak = 0 sftres = 0 mscan12 sleeping slprq = 1 slpak = 1 mscan12 running slprq = 0 slpak = 0 sleep request slprq = 1 slpak = 0 mcu ms can12 mcu or mscan12
low-power modes m68hc12b family data sheet, rev. 9.1 freescale semiconductor 253 the time when the mscan12 enters sleep mode depends on its activity. for instance, if it is transmitting, it continues to transmit until there are no more messages to be transmitted and then goes into sleep mode. if it is receiving, it waits for the end of this message and then goes into sleep mode. if it is neither transmitting nor receiv ing, it immediately goes into sleep mode. the application software must avoid setting up a transmission (by clearing one or more txe flag(s)) and immediately request sleep mode (by setting slprq). it then depends on the exact sequence of operations whether the mscan12 starts transmitting or goes into sleep mode directly. during sleep mode, the slpak flag is set. the a pplication software should use slpak as a handshake indication for the request (slprq) to go into sleep mode. when in sleep mode, the mscan12 stops its internal clocks. however, clocks to allow register acce sses still run. if the mscan12 is in bus-off state, it stops counting the 128 x 11 consecutive recessive bi ts due to the stopped clocks. the txcan pin stays in recessive state. if rxf = 1, the message can be read and rxf can be cleared. copying rxbg into rxfg doesn?t take place while in sleep mode. it is poss ible to access the transmit buffers and to clear the txe flags. no message abort takes place while in sleep mode. note the mscan12 leaves sleep mode (w akeup) when one of these occurs: bus activity occurs. mcu clears the slprq bit. mcu sets sftres. note the mcu cannot clear the slprq bit before the mscan12 is in sleep mode (slpak = 1). after wakeup, the mscan12 waits for 11 consecutive recessive bits to synchro nize to the bus. as a consequence, if the mscan12 is wakened by a can frame, this frame is not received. the receive message buffers (rxfg and rxbg) contain messages if they were received before sleep mode was entered. all pending actions are executed upon wake up: copying of rxbg into rxfg, message aborts, and message transmissions. if the msca n12 is still in bus-off state after sleep mode was left, it continues counting the 128 x 11 consecutive recessive bits. 16.7.2 mscan12 soft-reset mode in soft-reset mode, the mscan12 is stopped. regist ers can still be accessed. this mode is used to initialize the module configuration, bi t timing, and the can message filter. see 16.12.1 mscan12 module control register 0 for a complete description of the soft-reset mode. when setting the sftres bit, the mscan12 immediatel y stops all ongoing transmi ssions and receptions, potentially causing the ca n protocol violations. note the user is responsible for ensuring th at the mscan12 is not active when soft-reset mode is entered. the recommended procedure is to put the mscan12 into sleep mode before the sftres bit is set.
mscan12 controller m68hc12b family data sheet, rev. 9.1 254 freescale semiconductor 16.7.3 mscan12 power-down mode the mscan12 is in power-down mode when either of these occurs: cpu is in stop mode. cpu is in wait mode and the cswai bit is set. see 16.12.1 mscan12 module control register 0 and 16.12.2 mscan12 module control register 1 . when entering power-down mode, the mscan12 immediately stops all on-going transmissions and receptions, potentially causi ng can protocol violations. note the user should be careful that the mscan12 is not active when power-down mode is entered. the recommended procedure is to put the mscan12 into sleep mode before the stop instruction ? or the wai instruction, if cswai is set ? is executed. to protect the can bus system from fatal consequences of violations to this rule, the mscan12 will drive the txcan pin into recessive state. in power-down mode, no registers can be accessed. 16.7.4 programmable wakeup function the mscan12 can be programmed to apply a low-pass fi lter function to the rxcan input line while in sleep mode. see control bit wupm in the module control register, 16.12.2 mscan12 module control register 1 . this feature can be used to protect the msca n12 from wakeup due to short glitches on the can bus lines. such glitches can result from elec tromagnetic interference within noisy environments. 16.8 timer link the mscan12 generates a timer signal whenever a va lid frame has been received. because the can specification defines a frame to be valid if no erro rs occurred before the eof field has been transmitted successfully, the timer signal is generated right after the eof. a pulse of one bit time is generated. as the mscan12 receiver engine also receives the frames bei ng sent by itself, a timer signal also is generated after a successful transmission. the previously described timer signal can be routed into the on-chip timer interface module (tim). this signal is connected to the timer n channel m input (1) under the control of the timer link enable (tlnken) bit in the cmcr0. after timer n has been programmed to capture rising edge events, it can be used under software control to generate 16 bit-time stamps which can be stored with the received message. 16.9 clock system figure 16-7 shows the structure of the mscan12 clock generat ion circuitry. with th is flexible clocking scheme the mscan12 is able to handle can bus rates ranging from 10 kbps to 1 mbps. 1. the timer channel being used for th e timer link is integration dependent.
clock system m68hc12b family data sheet, rev. 9.1 freescale semiconductor 255 figure 16-7. clocking scheme the clock source bit (clksrc) in the msca n12 module control register (cmcr1) (see 16.12.3 mscan12 bus timing register 0 ) defines whether the mscan12 is connected to the output of the crystal oscillator (extali) or to a clock twice as fast as the system clock (eclk). the clock source has to be chosen so that the tigh t oscillator tolerance require ments (up to 0.4 percent) of the can protocol are met. additionally, for high can bus rates (1 mbps), a 50 percent duty cycle of the clock is required. for microcontrollers without the cgm module, cgmc anclk is driven from the crystal oscillator (extali). a programmable prescaler is used to generate out of mscanclk the time quanta (tq) clock. a time quantum is the atomic unit of time handled by the mscan12. a bit time is subdivided into three segments (1) : sync_seg ? this segment has a fixed length of one time quantum. signal edges are expected to happen within this section. time segment 1 ? this segment includes t he prop_seg and the phase_seg1 of the can standard. it can be programmed by setting the para meter tseg1 to consist of 4 to 16 time quanta. time segment 2 ? this segment represents t he phase_seg2 of the can standard. it can be programmed by setting the tseg2 parameter to be 2 to 8 time quanta. the synchronization jump width can be programmed in a range of 1 to 4 time quanta by setting the sjw parameter. these parameters can be set by progra mming the bus timing regi sters (cbtr0 and cbtr1). see 16.12.3 mscan12 bus timing register 0 and 16.12.4 mscan12 bus timing register 1 . note it is the user?s responsibility to make sure that the bit time settings are in compliance with the can standard. table 16-3 gives an overview on the can-conforming segment settings and the related parameter values. 1. for further explanation of the underlying co ncepts, refer to iso/di s 11519-1, section 10.3. mscan12 cgm sysclk extali cgmcanclk prescaler (1...64) time quanta clock clksrc clksrc f tq f cgmcanclk presc value t --------------------------------------- = bitrate f tq number of timequanta tt ----------------------------------------------------------------------------- =
mscan12 controller m68hc12b family data sheet, rev. 9.1 256 freescale semiconductor figure 16-8. segments within the bit time table 16-3. can standard compliant bit time segment settings time segment 1 tseg1 time segment 2 tseg2 synchronize jump width sjw 5.. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3 sync _seg time segment 1 time seg. 2 1 4 ... 16 2 ... 8 8... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) prop_seg + phase_seg1 (phase_seg2 transmit point
memory map m68hc12b family data sheet, rev. 9.1 freescale semiconductor 257 16.10 memory map the mscan12 occupies 128 bytes in the cpu12 memo ry space. the background receive buffer can be read only in test mode. 16.11 programmer?s model of message storage this subsection details the organization of the re ceive and transmit message buffers and the associated control registers. 16.11.1 message buff er organization figure 16-10 shows the organization of a single message buffer. for reasons of programmer interface simplification, the receive and transmit message buffers have the same register organization. each message buffer allocates 16 bytes in the memory map containing: 13-byte data structure which includes an identifier section (idrn), a data section (dsrn), and the data length register (dlr) transmit buffer priority register (tbpr) wh ich is only applicable for transmit buffers. see 16.11.5 transmit buffer priority register two unused bytes all bits of the 13-byte data structure are undefined out of reset. note the receive buffer can be read anytime but cannot be written. the transmit buffers can be read or written anytime. $0100 control registers 9 bytes $0108 $0109 reserved 5 bytes $010d $010e error counters 2 bytes $010f $0110 identifier filter 16 bytes $011f $0120 reserved 29 bytes $013c $013d port can registers 3 bytes $013f $0140 receive buffer (rxfg) $014f $0150 transmit buffer 0 (tx0) $015f $0160 transmit buffer 1 (tx1) $016f $0170 transmit buffer 2 (tx2) $017f figure 16-9. mscan12 memory map
mscan12 controller m68hc12b family data sheet, rev. 9.1 258 freescale semiconductor 16.11.2 identifier registers the bosch can 2.0a and 2.0b protocol specifications allow for two diffe rent sizes of message identifiers. the bosch can 2.0a specification requires an 11-bi t identifier in the message buffer and the bosch can 2.0b specification requires a 29-bit identifier in the message buffer. the resulting message buffers are referred to as standard and extended formats, respectively. the identifier registers (idrn) in the memory m ap can be configured to create either the 11-bit (idr10?idr0) identifier necessary for the standar d format or the 29-bit (idr28?idr0) identifier necessary for the extended format. figure 16-11 details the identifier structure used in the standard format while figure 16-12 details the identifier structure used in the extended format. id10/id28 is the most significant bit and is transmitted first on the bus duri ng the arbitration procedure. the priority of an identifier is defined to be the highest for the smallest binary number. address (1) register name 01x0 identifier register 0 01x1 identifier register 1 01x2 identifier register 2 01x3 identifier register 3 01x4 data segment register 0 01x5 data segment register 1 01x6 data segment register 2 01x7 data segment register 3 01x8 data segment register 4 01x9 data segment register 5 01xa data segment register 6 01xb data segment register 7 01xc data length register 01xd transmit buffer priority register (2) 01xe unused 01xf unused 1. x is 4, 5, 6, or 7 depend ing on which buffer, rxfg, tx0, tx1, or tx2, respectively. 2. not applicable for receive buffers. figure 16-10. message buffer organization
programmer?s model of message storage m68hc12b family data sheet, rev. 9.1 freescale semiconductor 259 srr ? substitute remote request bit this fixed recessive bit is used only in extended forma t. it must be set to 1 by the user for transmission buffers and will be stored as received on the can bus for receive buffers. ide ? id extended flag this flag indicates whether the extended or standard i dentifier format is applied in this buffer. in case of a receive buffer, the flag is set as received and indicates to the cpu how to process the buffer identifier registers. in case of a transmit buffer the flag indicates to the mscan12 what type of identifier to send. 0 = standard format (11 bit) 1 = extended format (29 bit) addr. (1) register name bit 7 6 5 4 3 2 1 bit 0 $01x0 identifier register 0 (idr0) read: id10 id9 id8 id7 id6 id5 id4 id3 write: reset: undefined out of reset $01x1 identifier register 1 (idr1) read: id2 id1 id0 rtr ide write: reset: undefined out of reset $01x2 identifier register 2 (idr2) read: write: reset: undefined out of reset $01x3 identifier register 3 (idr3) read: write: reset: undefined out of reset note 1. x is 4, 5, 6, or 7 depending on which buffer, rxfg, tx0, tx1, or tx3, respectively. = unimplemented figure 16-11. identifier mapping in the standard format addr. (1) register name bit 7 6 5 4 3 2 1 bit 0 $01x0 identifier register 0 (idr0) read: id28 id27 id26 id25 id24 id23 id22 id21 write: reset: undefined out of reset $01x1 identifier register 1 (idr1) read: id20 id19 id18 srr ide id17 id16 id15 write: reset: undefined out of reset $01x2 identifier register 2 (idr2) read: id14 id13 id12 id11 id10 id9 id8 id7 write: reset: undefined out of reset $01x3 identifier register 3 (idr3) read: id6 id5 id4 id3 id2 id1 id0 rtr write: reset: undefined out of reset note 1. x is 4, 5, 6, or 7 depending on which buffer, rxfg, tx0, tx1, or tx3, respectively. figure 16-12. identifier mapping in the extended format
mscan12 controller m68hc12b family data sheet, rev. 9.1 260 freescale semiconductor rtr ? remote transmission request flag this flag reflects the status of the remote transmission request bit in the can frame. in case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. in case of a transmit buffer, this flag defines the setting of the rtr bit to be sent. 0 = data frame 1 = remote frame 16.11.3 data length register the data length register (dlr) keeps t he data length field of the can frame. dlc3?dlc0 ? data length code bits the data length code contains the number of bytes (data byte count) of the respective message. at transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted bytes is always 0. the data byte count ranges from 0 to 8 for a data frame. table 16-4 shows the effect of setting the dlc bits. address: $01xc bit 7654321bit 0 read: dlc3 dlc2 dlc1 dlc0 write: reset: undefined out of reset = unimplemented note: x is 4, 5, 6, or 7 depending on which buffer, rxfg, tx0, tx1, or tx3, respectively. figure 16-13. data length register (dlr) table 16-4. data length codes data length code data byte count dlc3 dlc2 dlc1 dlc0 00000 00011 00102 00113 01004 01015 01106 01117 10008
programmer?s model of message storage m68hc12b family data sheet, rev. 9.1 freescale semiconductor 261 16.11.4 data segment registers the eight data segment registers (dsr0?dsr7) contain the data to be transmitted or being received. the number of bytes to be transmitted or received is determined by the data length code in the corresponding dlr. data is transmitted starting from the data segment register 0 (dsr0), beginning with the most significant bit (db7), and continuing until the number of bytes specified in the data length register (dlr) is complete. 16.11.5 transmit buffer priority register addr. (1) register name bit 7 6 5 4 3 2 1 bit 0 $01x4 data segment register 0 (dsr0) read: db7 db6 db5 db4 db3 db2 db1 db0 write: reset: undefined out of reset $01x5 data segment register 1 (dsr1) read: db7 db6 db5 db4 db3 db2 db1 db0 write: reset: undefined out of reset $01x6 data segment register 2 (dsr2) read: db7 db6 db5 db4 db3 db2 db1 db0 write: reset: undefined out of reset $01x7 data segment register 3 (dsr3) read: db7 db6 db5 db4 db3 db2 db1 db0 write: reset: undefined out of reset $01x8 data segment register 4 (dsr4) read: db7 db6 db5 db4 db3 db2 db1 db0 write: reset: undefined out of reset $01x9 data segment register 5 (dsr5) read: db7 db6 db5 db4 db3 db2 db1 db0 write: reset: undefined out of reset $01xa data segment register 6 (dsr6) read: db7 db6 db5 db4 db3 db2 db1 db0 write: reset: undefined out of reset $01xb data segment register 7 (dsr7) read: db7 db6 db5 db4 db3 db2 db1 db0 write: reset: undefined out of reset note 1.: x is 4, 5, 6, or 7 depending on which buffer, rxfg, tx0, tx1, or tx3, respectively. figure 16-14. data segment registers (dsrn) address: $01xd bit 7654321bit 0 read: prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 write: reset: unaffected by reset note 1. x is 5, 6, or 7 depending on which buffer tx0, tx1, or tx2, respectively. figure 16-15. transmit buffer priority register (tbpr)
mscan12 controller m68hc12b family data sheet, rev. 9.1 262 freescale semiconductor prio7?prio0? local priority this field defines the local priority of the associ ated message buffer. the local priority is used for the internal prioritization process of the mscan12 and is defined to be highest for the smallest binary number. the mscan12 implements this internal prioritization mechanism: ? all transmission buffers with a cleared txe flag participate in the prioritization right before the start of frame (sof) is sent. ? the transmission buffer with the lowest loca l priority field wins the prioritization. ? in case of more than one buffer having the same lowest priority, the message buffer with the lowest index number wins. 16.12 programmer?s mode l of control registers the programmer?s model has been laid out for maximum simplicity and efficiency. 16.12.1 mscan12 module control register 0 cswai ? can stops in wait mode bit 0 = the module is not affected during wait mode. 1 = the module ceases to be clocked during wait mode. synch ? synchronized status bit this bit indicates whether the mscan12 is synchroni zed to the can bus and as such can participate in the communication process. 0 = mscan12 is not synchronized to the can bus. 1 = mscan12 is synchronized to the can bus. tlnken ? timer enable flag this flag is used to establish a link betw een the mscan12 and the on-chip timer. see 16.8 timer link . 0 = port is connected to the timer input. 1 = mscan12 timer signal output is connected to the timer input. slpak ? sleep mode acknowledge flag this flag indicates whether the mscan12 is in m odule internal sleep mode. it shall be used as a handshake for the sleep mode request. see 16.7.1 mscan12 sleep mode . 0 = wakeup ? the mscan12 is not in sleep mode. 1 = sleep ? the mscan12 is in sleep mode. slprq ? sleep request, go to sleep mode flag this flag requests the mscan12 to go into an internal power-saving mode (see 16.7.1 mscan12 sleep mode ). 0 = wakeup ? the mscan12 will function normally. 1 = sleep request ? the msca n12 will go into sleep mode. address: $0100 bit 7654321bit 0 read: 0 0 cswai synch tlnken slpak slprq sftres write: reset:00100001 = unimplemented figure 16-16. mscan12 module control register 0 (cmcr0)
programmer?s model of control registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 263 sftres ? soft-reset bit when this bit is set by the cpu, the mscan12 immediately enters the soft-reset state. any on-going transmission or reception is aborted and synchronization to the bus is lost. these registers will go into and stay in the same state as out of hard reset: cmcr0, crflg, crier, ctflg, and ctcr. registers cmcr1, cbtr0, cbtr1, cidac, cidar0?cidar7, and cidmr0?cidmr7 can be written only by the cpu when the mscan12 is in soft-reset state. the values of the error counters are not affected by soft reset. when this bit is cleared by the cpu, the mscan12 will try to synchroni ze to the can bus. for example, if the mscan12 is not in bus-off state, it will be synchronized after 11 recessive bits on the bus; if the mscan12 is in bus-off state, it continues to wa it for 128 occurrences of 11 recessive bits. clearing sftres and writing to other bits in cmcr0 must be in separate instructions. 0 = normal operation 1 = mscan12 in soft-reset state 16.12.2 mscan12 module control register 1 loopb ? loop back self-test mode bit when this bit is set, the mscan12 performs an internal loop back which can be used for self-test operation. the bit stream output of the transmitter is fed back to the receiver. the rxcan input pin is ignored and the txcan output goes to the recessive st ate (1). in this state the mscan12 ignores the bit sent during the ack slot of the can frame acknow ledge field to ensure proper reception of its own message. both transmit and receive interrupts are generated. 0 = normal operation 1 = activate loop back self-test mode note the ack bit is added to the can frame by the protocol. for more information on the can frame and the ack bit, refer to the bosch can 2.0 specification. wupm ? wakeup mode flag this flag defines whether the integrated low-pass filter is applied to protect the mscan12 from spurious wakeups. see 16.7.4 programmable wakeup function . 0 = mscan12 will wake up the cpu after any recessive-to- dominant edge on the can bus. 1 = mscan12 will wake up the cpu only in the case of a dominant pulse on the bus which has a length of approximately t wup . address: $0101 bit 7654321bit 0 read:00000 loopb wupm clksrc write: reset:00000000 = unimplemented figure 16-17. mscan12 module control register 1 (cmcr1)
mscan12 controller m68hc12b family data sheet, rev. 9.1 264 freescale semiconductor clksrc ? mscan12 clock source flag this flag defines which clock source the mscan12 module is driven from (only for system with cgm module. see 16.9 clock system and figure 16-7 . 0 = mscan12 clock source is extali. 1 = mscan12 clock source is twice the frequency of eclk. note the cmcr1 register can be written only if the sftres bit in cmcr0 is set. 16.12.3 mscan12 bus timing register 0 sjw1 and sjw0 ? synchronization jump width bits the synchronization jump width defines the maxi mum number of time quanta (tq) clock cycles by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the bus (see table 16-5 ). brp5?brp0 ? baud rate prescaler bits these bits determine the time quanta (tq) clock, wh ich is used to build up th e individual bit timing, according to table 16-6 . note the cbtr0 register can be written only if the sftres bit in cmcr0 is set. address: $0102 bit 7654321bit 0 read: sjw1 sjw0 brp5 brp4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 figure 16-18. mscan12 bus timing register 0 (cbtr0) table 16-5. synchronization jump width sjw1 sjw0 synchronization jump width 0 0 1 tq clock cycle 0 1 2 tq clock cycles 1 0 3 tq clock cycles 1 1 4 tq clock cycles table 16-6. baud rate prescaler brp5 brp4 brp3 brp2 brp1 brp0 prescaler value (p) 000000 1 000001 2 000010 3 000011 4 :::::: : 111111 64
programmer?s model of control registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 265 16.12.4 mscan12 bus timing register 1 samp ? sampling bit this bit determines the number of samples of the serial bus to be taken per bit time. if set, three samples per bit are taken, the regular one (sample point) and two preceding samp les, using a majority rule. for higher bit rates, samp should be cleared, which means that only one sample will be taken per bit. 0 = one sample per bit 1 = three samples per bit. (1) tseg22?tseg10 ? time segment bits time segments within the bit time fix the number of clock cycles per bit time and the location of the sample point. see figure 16-7 . time segment 1 (tseg1) and time segment 2 (tseg2) are programmable as shown in table 16-8 . address: $0103 bit 7654321bit 0 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: reset:00000000 figure 16-19. mscan12 bus timing register 1 (cbtr1) 1. in this case, phase_seg1 must be at least two times quanta. table 16-7. time segment syntax sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode will transfer a new value to the can bus at this point. sample point a node in receive mode will sample the bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. table 16-8. time segment values tseg13 tseg12 tseg11 t seg10 time segment 1 0 0 0 0 1 tq clock cycle 0 0 0 1 2 tq clock cycles 0 0 1 0 3 tq clock cycles 0 0 1 1 4 tq clock cycles .... . 1 1 1 1 16 tq clock cycles tseg22 tseg21 tseg 20 time segment 2 0 0 0 1 tq clock cycle 0 0 1 2 tq clock cycles ... . 1 1 1 8 tq clock cycles
mscan12 controller m68hc12b family data sheet, rev. 9.1 266 freescale semiconductor the bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (tq) clock cycles per bit (as shown in table 16-8 ). note the cbtr1 register can be written only if the sftres bit in cmcr0 is set. 16.12.5 mscan12 recei ver flag register all bits of this register are read and clear only. a flag can be cleared by writing a 1 to the corresponding bit position. a flag can be cleared onl y when the condition which caused the setting is valid no longer. writing a 0 has no effect on the flag setting. every flag has an associated interrupt enable flag in the crier register. a hard or soft reset will clear the register. wupif ? wakeup interrupt flag if the mscan12 detects bus activity while in sle ep mode, it sets the wupif flag. if not masked, a wakeup interrupt is pending while this flag is set. 0 = no wakeup activity has be en observed while in sleep mode. 1 = mscan12 has detected activity on the bus and requested wakeup. rwrnif ? receiver warning interrupt flag this flag is set when the mscan12 goes into warning status due to the receive error counter (rec) exceeding 96 and neither one of the error interrupt flags nor the bus-off interrupt flag is set (1) . if not masked, an error interrupt is pending while this flag is set. 0 = no receiver warning status has been reached. 1 = mscan12 went into receiver warning status. twrnif ? transmitter warning interrupt flag this bit will be set when the mscan12 goes into warni ng status due to the transmit error counter (tec) exceeding 96 and neither one of the error interrupt flags nor the bus-off interrupt flag is set (2) . if not masked, an error interrupt is pending while this flag is set. 0 = no transmitter warning status has been reached. 1 = mscan12 went into transmitter warning status. address: $0104 bit 7654321bit 0 read: wupif rwrnif twrnif rerrif terrif boffif ovrif rxf write: reset:00000000 figure 16-20. mscan12 receiver flag register (crflg) 1. condition to set the flag: rwrnif = (96 rec 127) & rerrif & terrif & boffif 2. condition to set the flag: twrnif = (96 tec 127) & rerrif & terrif & boffif bittime presc value t f cgmcanclk --------------------------------------- number ? of timequanta tt =
programmer?s model of control registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 267 rerrif ? receiver error passive interrupt flag this flag is set when the mscan12 goes into error passive status due to the receive error counter (rec) exceeding 127 and the bus-off interrupt flag is not set (1) . if not masked, an error interrupt is pending while this flag is set. 0 = no receiver error passive status has been reached. 1 = mscan12 went into receiver error passive status. terrif ? transmitter error passive interrupt flag this flag is set when the mscan12 goes into error passive status due to the transmit error counter (tec) exceeding 127 and the bus-off interrupt flag is not set (2) . if not masked, an error interrupt is pending while this flag is set. 0 = no transmitter error passive status has been reached. 1 = mscan12 went into transmitter error passive status. boffif ? bus-off interrupt flag this flag is set when the mscan12 goes into bus-off status, due to the transmit error counter exceeding 255. it cannot be cleared before th e mscan12 has monitored 128 times 11 consecutive recessive bits on the bus. if not masked, an error interrupt is pending while this flag is set. 0 = no bus-off status has been reached. 1 = mscan12 went into bus-off status. ovrif ? overrun interrupt flag this flag is set when a data overrun condition occurs. if not masked, an error interrupt is pending while this flag is set. 0 = no data overrun has occurred. 1 = a data overrun has been detected. rxf ? receive buffer full flag the rxf flag is set by the mscan12 when a new message is available in the foreground receive buffer. this flag indicates whether the buffer is loaded with a correctly received message. after the cpu has read that message from the receive buffer, the rxf flag must be handshaken (cleared) to release the buffer. a set rxf flag prohibits the ex change of the background receive buffer into the foreground buffer. if not masked, a receive interrupt is pending while this flag is set. 0 = receive buffer is released (not full). 1 = receive buffer is full. a new message is available. note to ensure data integrity, no registers of the receive buffer shall be read while the rxf flag is cleared.the crflg register is held in the reset state when the sftres bit in cmcr0 is set. 1. condition to set the flag: rerrif = (128 rec 255) & boffif 2. condition to set the flag: terrif = (128 tec 255) & boffif
mscan12 controller m68hc12b family data sheet, rev. 9.1 268 freescale semiconductor 16.12.6 mscan12 receiver in terrupt enable register wupie ? wakeup interrupt enable bit 0 = no interrupt is generated from this event. 1 = a wakeup event results in a wakeup interrupt. rwrnie ? receiver warning interrupt enable bit 0 = no interrupt is generated from this event. 1 = a receiver warning status event results in an error interrupt. twrnie ? transmitter warning interrupt enable bit 0 = no interrupt is generated from this event. 1 = a transmitter warning status event results in an error interrupt. rerrie ? receiver error passive interrupt enable bit 0 = no interrupt is generated from this event. 1 = a receiver error passive status event results in an error interrupt. terrie ? transmitter error passive interrupt enable bit 0 = no interrupt is generated from this event. 1 = a transmitter error passive status event results in an error interrupt. boffie ? bus-off interrupt enable bit 0 = no interrupt is generated from this event. 1 = a bus-off event results in an error interrupt. ovrie ? overrun interrupt enable bit 0 = no interrupt is generated from this event. 1 = an overrun event results in an error interrupt. rxfie ? receiver full interrupt enable bit 0 = no interrupt is generated from this event. 1 = a receive buffer full (successful message reception) event results in a receive interrupt. note the crier register is held in the reset state when the sftres bit in cmcr0 is set. address: $0105 bit 7654321bit 0 read: wupie rwrnie twrnie rerrie terrie boffie ovrie rxfie write: reset:00000000 figure 16-21. mscan12 receiver interrupt enable register (crier)
programmer?s model of control registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 269 16.12.7 mscan12 transm itter flag register the abort acknowledge flags are read only. the transmi tter buffer empty flags are read and clear only. a flag can be cleared by writing a 1 to the corresponding bit pos ition. writing a 0 has no ef fect on the flag setting. each transmitter buffer empty flag has an associated inte rrupt enable bit in the ctcr register. a hard or soft reset resets the register. abtak2?abtak0 ? abort acknowledge flag this flag acknowledges that a message has been aborted due to a pending abort request from the cpu. after a particular message buffer has been flagged empty, this flag can be used by the application software to identify whether the mess age has been aborted successfully or has been sent in the meantime. the abtakx flag is cleared im plicitly whenever the corresponding txe flag is cleared. 0 = the message has not been aborted; it has been sent. 1 = the message has been aborted. txe2?txe0 ?transmitter buffer empty flag this flag indicates that the associated transmit message buffer is empty, thus not scheduled for transmission. the cpu must handshake (clear) the flag after a message has been set up in the transmit buffer and is due for transmission. the mscan12 sets the flag after the message has been sent successfully. the flag is also set by t he mscan12 when the transmission request was aborted successfully due to a pending abort request. see 16.12.8 mscan12 transmitter control register . if not masked, a transmit interrupt is pending while this flag is set. clearing a txex flag also clears the correspon ding abtakx flag. when a txex flag is set, the corresponding abtrqx bit is cleared. see 16.12.8 mscan12 transmitter control register . 0 = the associated message buffer is full (loaded with a message due for transmission). 1 = the associated message buffer is empty (not scheduled). note to ensure data integrity, no registers of the transmit buffers should be written to while the associated txe flag is cleared.the ctflg register is held in the reset state if the sftres bit cmcr0 is set. address: $0106 bit 7654321bit 0 read: 0 abtak2 abtak1 abtak0 0 txe2 txe1 txe0 write: reset:00000111 = unimplemented figure 16-22. mscan12 transmitter flag register (ctflg)
mscan12 controller m68hc12b family data sheet, rev. 9.1 270 freescale semiconductor 16.12.8 mscan12 transmit ter control register abtrq2?abtrq0 ? abort request bits the cpu sets an abtrqx bit to request that a sche duled message buffer (txex = 0) shall be aborted. the mscan12 grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). when a message is aborted, the associated txe and the abort acknowledge flag (abtak) (see 16.12.7 mscan12 transmitter flag register ) are set and an txe interrupt is generated if enabled. the cpu cannot reset abtrqx. abtrqx is cleared implicitly whenever the associated txe flag is set. 0 = no abort request 1 = abort request pending note the software must not clear one or more of the txe flags in ctfgl and simultaneously set the respective abtrq bit(s). txeie2?txeie0 ? transmitter empty interrupt enable bits 0 = no interrupt will be generated from this event. 1 = a transmitter empty (transmit buffer available for transmission) event will result in a transmitter empty interrupt. note the ctcr register is held in the reset state when the sftres bit in cmcr0 is set. 16.12.9 mscan12 identifier acceptance control register address: $0107 bit 7654321bit 0 read: 0 abtrq2 abtrq1 abtrq0 0 txeie2 txeie1 txeie0 write: reset:00000000 = unimplemented figure 16-23. mscan12 transmitter control register (ctcr) address: $0108 bit 7654321bit 0 read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: reset:00000000 = unimplemented figure 16-24. mscan12 identifier acceptance control register (cidac)
programmer?s model of control registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 271 idam1 and idam0? identifier acceptance mode flags the cpu sets these flags to define the i dentifier acceptance filter organization. see 16.4 identifier acceptance filter . table 16-8 summarizes the different settings. in filter closed mode, no messages are accepted so that the foreground buffer is never reloaded. idhit2?idhit0? identifier acceptance hit indicator flags the mscan12 sets these flags to indi cate an identifier acceptance hit. see 16.4 identifier acceptance filter . table 16-8 summarizes the different settings. the idhit indicators are always related to the message in the foreground buffer. when a message gets copied from the background to the foregrou nd buffer, the indicators are updated as well. note the cidac register can be written only if the sftres bit in cmcr0 is set. 16.12.10 mscan12 receive error counter this register reflects the status of the mscan1 2 receive error counter. the register is read only. table 16-9. identifier acceptance mode settings idam1 idam0 identifier acceptance mode 0 0 two 32-bit acceptance filters 0 1 four 16-bit acceptance filters 1 0 eight 8-bit acceptance filters 1 1 filter closed table 16-10. identifier acceptance hit indication idhit2 idhit1 idhit0 iden tifier acceptance hit 0 0 0 filter 0 hit 0 0 1 filter 1 hit 0 1 0 filter 2 hit 0 1 1 filter 3 hit 1 0 0 filter 4 hit 1 0 1 filter 5 hit 1 1 0 filter 6 hit 1 1 1 filter 7 hit address: $010e bit 7654321bit 0 read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: reset:00000000 = unimplemented figure 16-25. mscan12 receive error counter (crxerr)
mscan12 controller m68hc12b family data sheet, rev. 9.1 272 freescale semiconductor 16.12.11 mscan12 transm it error counter this register reflects the status of the mscan1 2 transmit error counter. the register is read only. note both error counters may be read only when in sleep or soft-reset mode. 16.12.12 mscan12 identifi er acceptance registers on reception, each message is written into the backg round receive buffer. the cpu is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message will be overwritten by the next message (dropped). the acceptance registers of the mscan12 are applied on the idr0 to idr3 registers of incoming messages in a bit-by-bit manner. for extended identifiers, all four acceptance and mask registers are applied. for standard identifiers only the first two (cidmr0/cidmr1 and cidar0/cidar1) are applied. address: $010f bit 7654321bit 0 read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: reset:00000000 = unimplemented figure 16-26. mscan12 transmit error counter (ctxerr) address: $0110 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset address: $0111 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset address: $0112 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset address: $0113 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset figure 16-27. first bank mscan12 identifier acceptance registers (cidar0?cidar3)
programmer?s model of control registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 273 ac7?ac0 ? acceptance code bits ac7?ac0 comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corresponding identifier mask register. note the cidar0-cidar7 registers can be wr itten only if the sftres bit in cmcr0 is set. 16.12.13 mscan12 identi fier mask registers the identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. to receive standard identifiers in 32-bit filter mode, the last three bits (am2?am0) in the mask registers cidmr1 and cidmr5 must be programmed to don?t care. to receive standard identifiers in 16 bit filter mode the last th ree bits (am2?am0) in the mask registers cidmr1, cidmr3, cidmr5, and cidmr7 must be programmed to don?t care. address: $0118 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset address: $0119 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset address: $011a bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset address: $011b bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset figure 16-28. second bank mscan12 identifier acceptance registers (cidar4?cidar7)
mscan12 controller m68hc12b family data sheet, rev. 9.1 274 freescale semiconductor address: $0114 bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset address: $0115 bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset address: $0116 bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset address: $0117 bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset figure 16-29. first bank mscan12 identifier mask registers (cidmr0?cidmr3) address: $011c bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset address: $011d bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset address: $011e bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset address: $011f bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset figure 16-30. second bank mscan12 identifier mask registers (cidmr4?cidmr7)
programmer?s model of control registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 275 am7?am0 ? acceptance mask bits if a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifi er bit before a match will be detected. the message will be accepted if all such bits match. if a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register will not af fect whether or not the message is accepted. 1 = ignore corresponding acceptance code register bit. 0 = match corresponding acceptance code register and identifier bits. note the cidmr0?cidmr7 registers can be written only if the sftres bit in cmcr0 is set. 16.12.14 mscan12 port can control register these bits control pins 7?2 of port can control regi ster. pins 1 and 0 are reserved for the rxcan (input only) and txcan (output only) pins. puecan ? pullup enable port can bit 0 = pull mode disabled for port can 1 = pull mode enabled for port can rdpcan ? reduced drive port can 0 = reduced drive disabled for port can 1 = reduced drive enabled for port can 16.12.15 mscan12 port can data register pcan7?pcan2 ? port can data bits writing to pcanx stores the bit value in an internal bit memory. this value is driven to the respective pin only if ddrcanx = 1. reading pcanx returns: value of the internal bit memory driven to the pin, if ddrcanx = 1 value of the respective pin, if ddrcanx = 0 reading bits 1 and 0 returns the value of the txcan and rxcan pins, respectively. address: $013d bit 7654321bit 0 read:000000 puecan rdpcan write: reset:00000000 = unimplemented figure 16-31. mscan12 port can control register (pctlcan) address: $013e bit 7654321bit 0 read: pcan7 pcan6 pcan5 pcan4 pcan2 pcan2 txcan rxcan write: reset: unaffected by reset = unimplemented figure 16-32. mscan12 port can data register (portcan)
mscan12 controller m68hc12b family data sheet, rev. 9.1 276 freescale semiconductor 16.12.16 mscan12 port can data direction register ddrcan7?ddrcan2 ? data direction port can bits 0 = respective input/output (i/o ) pin is configured for input. 1 = respective i/o pin is configured for output. address: $013f bit 7654321bit 0 read: ddrcan7 ddrcan6 ddrcan5 ddrcan4 ddrcan3 ddrcan2 00 write: reset:00000000 = unimplemented figure 16-33. mscan12 port can data direction register (ddrcan)
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 277 chapter 17 analog-to-digital converter (atd) 17.1 introduction the atd is an 8-channel, 10-bit, multiplexed-input , successive-approximation, analog-to-digital converter, accurate to 2 least significant bit (lsb). it does not r equire external sample and hold circuits because of the type of charge redistribution tech nique used. the atd conver ter timing is synchronized to the system p clock. the atd module consists of a 16-word (32-byte) memory-mapped control register block used for control, te sting, and configuration. 17.2 functional description a single conversion sequence consists of four or ei ght conversions, depending on the state of the select 8-channel mode (s8cm) bit when atdctl5 is written. there are eight basic conversion modes. in the non-scan modes, the scf bit is set after the sequenc e of four or eight conversions has been performed and the atd module halts. in the scan modes, the scf bi t is set after the first sequence of four or eight conversions has been performed, and the atd module cont inues to restart the sequence. in both modes, the ccf bit associated with each register is set when that register is loaded with the appropriate conversion result. that flag is cleared automatically when that result register is read. the conversions are started by writing to the control registers.
analog-to-digital converter (atd) m68hc12b family data sheet, rev. 9.1 278 freescale semiconductor figure 17-1. atd block diagram atd0 sar rc dac array and comparator v dda v ssa v rl v rh analog mux and sample buffer an7/pad7 an6/pad6 an5/pad5 an4/pad4 an3/pad3 an2/pad2 an1/pad1 an0/pad0 atd1 atd2 atd3 atd4 atd5 atd6 atd7 mode and timing control clock select/prescale port ad data input register amplifier internal bus
atd registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 279 17.3 atd registers this section describes the atd registers. 17.3.1 atd cont rol register 0 read: anytime write: anytime note writes to this register abor t the current conversion sequence. 17.3.2 atd cont rol register 1 read: special mode only write: has no meaning 17.3.3 atd cont rol register 2 read: anytime write: anytime except ascif bit, which cannot be written the atd control register 2 (atdctl2) is used to se lect the power-up mode, interrupt control, and freeze control. note writing to this register aborts the current conversion sequence. address: $0060 bit 7654321bit 0 read: 00000000 write: reset:00000000 figure 17-2. atd control register 0 (atdctl0) address: $0061 bit 7654321bit 0 read: 00000000 write: reset:00000000 figure 17-3. reserved (atdctl1) address: $0062 bit 7654321bit 0 read: adpu affc awai 000 ascie ascif write: reset:00000000 = unimplemented figure 17-4. atd control register 2 (atdctl2)
analog-to-digital converter (atd) m68hc12b family data sheet, rev. 9.1 280 freescale semiconductor adpu ? atd disable bit software can disable the clock signal to the atd and power down the analog circuits to reduce power consumption. when reset to 0, the adpu bit abor ts any conversion sequence in progress. because the bias currents to the analog circuits are turned off, the atd requires a period of recovery time to stabilize the analog circuits after setting the adpu bit. 0 = disables the atd, including the analog section for reduction in power consumption 1 = allows the atd to function normally affc ? atd fast flag clear bit 0 = atd flag clearing operates normally (read the st atus register before reading the result register to clear the associated ccf bit). 1 = changes all atd conversion complete flags to a fast clear sequence. any access to a result register (atd0?atd7) will cause the associated ccf flag to clear automatically if it was set at the time. awai ? atd stop in wait mode bit 0 = atd continues to run when the mcu is in wait mode. 1 = atd stops to save power when the mcu is in wait mode. ascie ? atd sequence complete interrupt enable bit 0 = disables atd interrupt 1 = enables atd interrupt on sequence complete ascif ? atd sequence complete interrupt flag cannot be written in any mode. 0 = no atd interrupt occurred 1 = atd sequence complete 17.3.4 adt cont rol register 3 read: anytime write: anytime the atd control register 3 (atdctl3) is used to se lect the power-up mode, interrupt control, and freeze control. note writing to this register aborts any current conversion sequence and suspends module operation at breakpoint. address: $0063 bit 7654321bit 0 read:000000 frz1 frz0 write: reset:00000000 = unimplemented figure 17-5. atd control register 3 (atdctl3)
atd registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 281 frz1 and frz0 ? background debug (freeze) enable bits when debugging an application, it is useful in many cases to have the atd pause when a breakpoint is encountered. these two bits determine how the atd will respond when background debug mode becomes active. see table 17-1 . 17.3.5 atd cont rol register 4 the atd control register 4 (atdctl4) selects the cloc k source and sets up the prescaler. writes to the atd control registers initiate a new conversion se quence. if a write occurs wh ile a conversion is in progress, the conversion is aborted and atd ac tivity halts until a write to atdctl5 occurs. s10bm ? atd 10-bit mode control bit 0 = 8-bit operation 1 = 10-bit operation smp1 and smp0 ? select sample time bits these bits are used to select one of four sample times after the buffered sample and transfer has occurred. see table 17-2 . prs4?prs0 ? select divide-by factor for atd p-clock prescaler bits the binary value written to these bits (1 to 31) se lects the divide-by factor for the modulo counter-based prescaler. the p clock is divided by this value plus one, and then fed into a divide-by-two circuit to generate the atd module clock. the divide-by-two ci rcuit ensures symmetry of the output clock signal. table 17-1. atd response to background debug enable frz1 frz0 atd response 0 0 continue conversions in active background mode 01reserved 1 0 finish current conversion, then freeze 1 1 freeze when bdm is active address: $0064 bit 7654321bit 0 read: s10bmsmp1smp0prs4prs3prs2prs1prs0 write: reset:00000001 figure 17-6. atd control register 4 (atdctl4) table 17-2. final sample time selection smp1 smp0 final sample time total 8-bit conversion time total 10-bit conversion time 0 0 2 atd clock periods 18 atd clock periods 20 atd clock periods 0 1 4 atd clock periods 20 atd clock periods 22 atd clock periods 1 0 8 atd clock periods 24 atd clock periods 26 atd clock periods 1 1 16 atd clock periods 32 atd clock periods 34 atd clock periods
analog-to-digital converter (atd) m68hc12b family data sheet, rev. 9.1 282 freescale semiconductor clearing these bits causes the prescale value to def ault to 1 which results in a divide-by-two prescale factor. this signal is then fed into the divide-by-two logic. the reset state divides the p clock by a total of four and is appropriate for nominal operation at a bus rate of between 2 mhz and 8 mhz. table 17-3 shows the divide-by operation and the appropriate range of system clock frequencies. 17.3.6 atd cont rol register 5 read: anytime write: anytime the atd control register 5 is used to select the c onversion modes, the conversion channel(s), and initiate conversions. a write to atdctl5 initiates a new conversion sequenc e. if a conversion sequence is in progress when a write occurs, that sequence is aborted and the scf and ccf bits are reset. s8cm ? select 8 channel mode bit 0 = conversion sequence cons ists of four conversions. 1 = conversion sequence consists of eight conversions. table 17-3. clock prescaler values prescale value total divisor max p clock (1) 1. maximum conversion frequency is 2 mhz. maximum p clock divisor value becomes maximum conversion rate that can be used on this atd module. min p clock (2) 2. minimum conversion frequency is 500 khz. minimum p clock divisor value becomes minimum conversion rate th at this atd can perform. 00000 2 4 mhz 1 mhz 00001 4 8 mhz 2 mhz 00010 6 8 mhz 3 mhz 00011 8 8 mhz 4 mhz 00100 10 8 mhz 5 mhz 00101 12 8 mhz 6 mhz 00110 14 8 mhz 7 mhz 00111 16 8 mhz 8 mhz 01xxx do not use 1xxxx address: $0065 bit 7654321bit 0 read: s8cm scan mult cd cc cb ca write: reset:00000000 = unimplemented figure 17-7. atd control register 5 (atdctl5)
atd registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 283 scan ? enable continuous channel scan bit when a conversion sequence is initiat ed by a write to the atdctl register, the user has a choice of performing a sequence of four (or eight, depending on the s8cm bit) conversions or continuously performing four (or ei ght) conversion sequences. 0 = single conversion sequence 1 = continuous conversion sequences (scan mode) mult ? enable multichannel conversion bit 0 = atd sequencer runs all four or eight conversions on a single input channel selected via the cd, cc, cb, and ca bits. 1 = atd sequencer runs each of t he four or eight conversions on sequential channels in a specific group. refer to table 17-4 . cd, cc, cb, and ca ? channel select for conversion bits table 17-4. multichannel mode result register assignment s8cm cd cc cb ca channel signal result in adrx if mult = 1 000 0 0an0 adr0 0 1an1 adr1 1 0an2 adr2 1 1an3 adr3 001 0 0an4 adr0 0 1an5 adr1 1 0an6 adr2 1 1an7 adr3 010 0 0reserved adr0 0 1reserved adr1 1 0reserved adr2 1 1reserved adr3 011 0 0 v rh adr0 0 1 v rl adr1 1 0 (v rh + v rl )/2 adr2 1 1test/reserved adr3 10 0 0 0an0 adr0 0 0 1an1 adr1 0 1 0an2 adr2 0 1 1an3 adr3 1 0 0an4 adr4 1 0 1an5 adr5 1 1 0an6 adr6 1 1 1an7 adr7
analog-to-digital converter (atd) m68hc12b family data sheet, rev. 9.1 284 freescale semiconductor 17.3.7 atd status registers read: normally anytime write: in special mode, the scf bit and the ccf bits may also be written. the atd status registers contain the flags indicating the completion of atd conversions. scf ? sequence complete flag this bit is set at the end of the conversion sequen ce when in the single conversion sequence mode (scan = 0 in atdctl5) and is set at the end of the first conversion sequence when in the continuous conversion mode (scan = 1 in atdctl5). when affc = 0, scf is cleared when a write is performed to atdctl5 to initiate a new conversion sequence. when affc = 1, scf is cleared after the first result register is read. 11 0 0 0reserved adr0 0 0 1reserved adr1 0 1 0reserved adr2 0 1 1reserved adr3 1 0 0 v rh adr4 1 0 1 v rl adr5 1 1 0 (v rh + v rl )/2 adr6 1 1 1test/reserved adr7 shaded bits are ?don?t care? if mult = 1 and th e entire block of four or eight channels makes up a conversion sequence. when mult = 0, all four bits (cd, cc, cb, and ca) must be specified and a conversion sequence consists of four or eight consecutive conversions of the single specified channel. address: $0066 bit 7654321bit 0 read:scf0000cc2cc1cc0 write: reset:00000000 figure 17-8 address: $0067 bit 7654321bit 0 read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: reset:00000000 = unimplemented figure 17-9. atd status register (atdstat) table 17-4. multichannel mode result register assignment (continued) (continued) s8cm cd cc cb ca channel signal result in adrx if mult = 1
atd registers m68hc12b family data sheet, rev. 9.1 freescale semiconductor 285 cc2?cc0 ? conversion counter bits for current 4 or 8 conversions this 3-bit value reflects the contents of the conversion counter pointer in a four or eight count sequence. this value also reflects which result regi ster is written next, indicating which channel is currently being converted. ccf7?ccf0 ? conversion complete flags each ccf bit is associated with an individual atd result register. for each register, this bit is set at the end of conversion for the associated atd channel and remains set until that atd result register is read. it is cleared at that time if affc bit is se t, regardless of whether a status register read has been performed (for example, a status register read is not a pre-qualifier for the clearing mechanism when affc = 1). otherwise, the status register must be read to clear the flag. 17.3.8 atd test registers read: special modes only write: special modes only the test registers control various special modes which are used during manufacturing. in the normal modes, reads of the test register return 0 and writes have no effect. sar9?sar0 ? sar data bits reads of this byte return the current value in the sar. writes to this byte change the sar to the value written. bits sar9?sar0 reflect the 10 sar bits used during the resolution process for an 10-bit result. rst ? module reset bit when set, this bit causes all registers and activity in the module to assume the same state as out of power-on reset (except for adpu bit in atdctl2, which remains set, allowing the atd module to remain enabled). tstout ? multiplex output of tst3?tst0 (factory use) tst3?tst0 ? test bits 3 to 0 (reserved) selects one of 16 reserved factory testing modes address: $0068 bit 7654321bit 0 read: sar9 sar8 sar7 sar6 sar5 sar4 sar3 sar2 write: reset:00000000 figure 17-10 address: $0069 bit 7654321bit 0 read: sar1 sar0 rst tstout tst3 tst2 tst1 tst0 write: reset:00000000 figure 17-11. atd test register (atdstat)
analog-to-digital converter (atd) m68hc12b family data sheet, rev. 9.1 286 freescale semiconductor 17.3.9 port ad da ta input register read: anytime write: has no meaning or effect pad7?pad0 ? port ad data input bits after reset, these bits reflect the state of the input pins. pad7?pad0 may be used for general-purpose digital input. when the software reads portad, it obtains the digital levels that appear on the corresp onding port ad pins. pins with signals not meeting v il or v ih specifications will have an indeterminate value. 17.3.10 atd result registers address: $006f bit 7654321bit 0 read: pad7 pad6 pad5 pad4 pad3 pad2 pad1 pad0 write: reset: after reset, reflect the state of the inputs pins = unimplemented figure 17-12. port ad data input register (portad) adrx0h: adrx1h: adrx2h: adrx3h: adrx4h: adrx5h: adrx6h: adrx7h: $0070 $0072 $0074 $0076 $0078 $007a $007c $007e bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: undefined = unimplemented figure 17-13. atd result registers high adrx0l: adrx1l: adrx2l: adrx3l: adrx4l: adrx5l: adrx6l: adrx7l: $0071 $0073 $0075 $0077 $0079 $007b $007d $007f bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: undefined = unimplemented figure 17-14. atd result registers low
atd mode operation m68hc12b family data sheet, rev. 9.1 freescale semiconductor 287 read: anytime write: has no meaning or effect adrxh[15:8]?adrxh[7:0] ? atd conversion result bits the reset condition for these registers is undefined. these bits contain the left-justifi ed, unsigned result from the atd c onversion. the channel from which this result was obtained is dependant on the conv ersion mode selected. these registers are always read-only in normal mode. 17.4 atd mo de operation stop causes all clocks to halt (if the s bit in the ccr is 0). the sys tem is placed in a minimum-power standby mode. this aborts any c onversion sequence in progress. during stop recovery, the atd must delay for the stop recovery time (t sr ) before initiating a new atd conversion sequence. wait atd conversion continues unless the awai bit in atdctl2 register is set. bdm debug options available as set in register atdctl3. user atd continues running unless adpu is cleared. adpu atd operations are stopped if adpu = 0, but registers are accessible. 17.5 using the atd to me asure a potentiometer signal this exercise allows the student to utilize the at d on the hc12 to measure a potentiometer signal output routed from the udlp1 board to the hc12 atd pin pad6. first the atdctl registers are initialized. a delay loop of 100 s is then executed. the resolution is set up followed by a conversion set up on channel 6. after waiting for the status bit to set, the result goes to the d accumulator. if the program is working properly, a different value should be found in the d ac cumulator as the left potentiometer is varied for each execution of the program. 17.5.1 equipment for this exercise, use the m6 8hc912b32evb emulation board. 17.5.2 code listing note a comment line is deliminted by a se mi-colon. if there is no code before comment, an ?;? must be placed in the first column to avoid assembly errors.
analog-to-digital converter (atd) m68hc12b family data sheet, rev. 9.1 288 freescale semiconductor ; ---------------------------------------------------------------------- ; main program ; ---------------------------------------------------------------------- org $7000 ; 16k on-board ram, user code data area, ; start main program at $7000 main: bsr init ; branch to init subroutine to initialize atd bsr convert ; branch to convert subroutine for conversion done: bra done ; branch to self, convenient place for breakpoint ; ---------------------------------------------- ; subroutine init: initialize atd ; ; ---------------------------------------------- init: ldaa #$80 ; allow atd to function normally, staa atdctl2 ; atd flags clear normally & disable interrupts bsr delay ; delay (100 us) for wait delay time. ldaa #$00 ; select continue conversion in bgnd mode staa atdctl3 ; ignore freeze in atdctl3 ldaa #$01 ; select final sample time = 2 a/d clocks staa atdctl4 ; prescaler = div by 4 (prs4:0 = 1) rts ; return from subroutine ; ---------------------------------------------- ; subroutine convert: ; ; ---------------------------------------------- ; set-up atd, make single conversion and store the result to a memory location. ; configure and start a/d conversion ; analog input signal: on port ad6 ; convert: using single channel, non-continuous ; the result will be located in adr2h convert: ldaa #$06 ; initializes atd scan=0,mult=0, pad6, ; ; write clears flag staa atdctl5 ; 4 conversions on a single conversion ; ; sequence, wtconv: brclr atdstath,#$80,wtconv ; wait for sequence complete flag ldd adr2h ; loads conversion result(adr2h) ; ; into accumulator bra convert ; continuously updates results rts ; return from subroutine ;* ------------------------------- ;* subroutine delay 100 us * ;* ------------------------------- ; delay required for atd converter to stabilize (100 usec) ldaa #$c8 ; load accumulator with "100 usec delay value" delay: deca ; decrement acc bne delay ; branch if not equal to zero rts ; return from subroutine end ; end of program
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 289 chapter 18 development support 18.1 introduction development support involves complex interactions between mcu resources and external development systems. this section concerns instruction queue and queue tracking signals, background debug mode, breakpoints, and instruction tagging. 18.2 instruction queue it is possible to monitor cpu activity on a cycle -by-cycle basis for debugging.the cpu12 instruction queue provides at least three bytes of program inform ation to the cpu when instruction execution begins. the cpu12 always completely finishes executing an instruction before beginning to execute the next instruction. status signals ipipe1 and ipipe0 provide information about data movement in the queue and indicate when the cpu begins to execute instructi ons. information available on the ipipe1 and ipipe0 pins is time multiplexed. external circuitry can latch data movement information on rising edges of the e-clock signal; execution start inform ation can be latched on falling edges. table 18-1 shows the meaning of data on the pins. table 18-1. ipipe decoding data movement ? ipipe[1:0] captur ed at rising edge of e clock (1) 1. refers to data that was on the bus at the previous e falling edge. ipipe[1:0] mnemonic meaning 0:0 ? no movement 0:1 lat latch data from bus 1:0 ald advance queue and load from bus 1:1 all advance queue and load from latch execution start ? ipipe[1:0] captured at falling edge of e clock (2) 2. refers to bus cycle starti ng at this e falling edge. ipipe[1:0] mnemonic meaning 0:0 ? no start 0:1 int start interrupt sequence 1:0 sev start even instruction 1:1 sod start odd instruction
development support m68hc12b family data sheet, rev. 9.1 290 freescale semiconductor program information is fetched a few cycles before it is used by the cpu. to monitor cycle-by-cycle cpu activity, it is necessary to externally reconstruct w hat is happening in the instruction queue. internally, the mcu only needs to buffer the data from program fetches . for system debug it is necessary to keep the data and its associated address in the reconstructed instruction queue. the raw signals required for reconstruction of the queue are addr, data, r/w , eclk, and status signals ipipe1 and ipipe0. the instruction queue consists of two 16-bit queue st ages and a holding latch on the input of the first stage. to advance the queue means to move the word in the first stage to the second stage and move the word from either the holding latch or the data bus input buffer into the first stage. to start even (or odd) instruction means to execute the opcode in the high-order (or low-order) byte of the second stage of the instruction queue. 18.3 background debug mode (bdm) background debug mode (bdm) is used for system deve lopment, in-circuit testing, field testing, and programming. bdm is implemented in on-chip hard ware and provides a full set of debug options. because bdm control logic does not reside in the cpu, bdm hardware commands can be executed while the cpu is operating normally. the control logic generally uses cpu dead cycles to execute these commands, but can steal cycles fr om the cpu when necessary. other bdm commands are firmware based and require the cpu to be in active background mode for execution. while bdm is active, the cpu executes a firmware program located in a small on-ch ip rom that is available in the standard 64-kbyte memory map only while bdm is active. the bdm control logic communicates serially with an external host development system, via the bkgd pin. this single-wire approach minimizes the number of pins needed for development support. 18.3.1 bdm serial interface the bdm serial interface requires the external controller to generate a falling edge on the bkgd pin to indicate the start of each bit time. the external c ontroller provides this falling edge whether data is transmitted or received. bkgd is a pseudo-open-drain pin that can be driven either by an external controller or by the mcu. data is transferred msb first at 16 e-clock cycles per bit ( nominal speed). the interface times out if 512 e-clock cycles occur between falling edges from the host. the hardware clears the command register when this timeout occurs. the bkgd pin can receive a high or low level or transmit a high or low level. figure 18-1 , figure 18-2 , and figure 18-3 show timing for each of these cases. interf ace timing is synchronous to mcu clocks but asynchronous to the external host. the internal cloc k signal is shown for reference in counting cycles.
background debug mode (bdm) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 291 figure 18-1 shows an external host transmitting a logic 1 or 0 to the bkgd pin of a target m68hc12 mcu. the host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. ten target e cycles later, the target senses the bit level on the bkgd pin. typically, the host actively drives the pseudo-open-drain bkgd pin during host-to-target transmissions to speed up rising edges. since the target does not drive the bkgd pin during this period, there is no need to treat the line as an open-drain signal during host-to-target transmissions. figure 18-1. bdm host to target serial bit timing figure 18-2 shows the host receiving a logic 1 from the ta rget mcu. since the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the perceived start of the bit time in the target mcu. the host holds the bkgd pin low long enough for the target to recognize it (at least two target e cycles). the host must release the low drive before the target mcu drives a brief active-high speed-up pulse seven cycles after the perceived start of the bit time. the host should sample the bit level about 10 cycles after it started the bit time. figure 18-2. bdm target to host serial bit timing (logic 1) earliest start of next bit target senses bit 10 cycles synchronization uncertainty e clock target mcu host transmit 1 host transmit 0 perceived start of bit time high impedance high impedance high impedance earliest start of next bit r-c rise 10 cycles 10 cycles host samples bkgd pin perceived start of bit time bkgd pin e clock target mcu host drive to bkgd pin target mcu speedup pulse
development support m68hc12b family data sheet, rev. 9.1 292 freescale semiconductor figure 18-3 shows the host receiving a logic 0 from the ta rget mcu. since the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by the target mcu. the host initiates the bit time but the target mcu finishes it. since the target wants the host to receive a logic 0, it drives the bkgd pin low for 13 e-clock cycles, then briefly drives it high to speed up the rising edge. the host samples the bit level about 10 cycles after starting the bit time. figure 18-3. bdm target to host serial bit timing (logic 0) 18.3.2 enabling bdm firmware commands bdm is available in all operating modes, but mu st be made active before firmware commands can be executed. bdm is enabled by setting the enbdm bit in the bdm status register via the single-wire interface (using a hardware command; write_bd_byte at $ff01). bdm must then be activated to map bdm registers and rom to addresses $ff00 to $ ffff and to put the mcu in active background mode. after the firmware is enabled, bdm can be activa ted by the hardware background command, by the bdm tagging mechanism, or by the cpu bgnd instructi on. an attempt to activate bdm before firmware has been enabled causes the mcu to resume normal instruction execution after a brief delay. bdm becomes active at the next instruction boundary following executio n of the bdm background command, but tags activate bdm before a tagged instruction is executed. in special single-chip mode, background operation is enabled and active immediately out of reset. this active case replaces the m68hc11 boot function an d allows programming a system with blank memory. while bdm is active, a set of bdm control registers is mapped to addresses $ff00 to $ff06. the bdm control logic uses these registers which can be read anytime by bdm logic, not user programs. refer to 18.3.4 bdm registers for detailed descriptions. some on-chip peripherals have a bdm control bit whic h allows suspending the peripheral function during bdm. for example, if the timer control is enabled, t he timer counter is stopped while in bdm. once normal program flow is continued, the timer counter is re-enabled to simulate real-time operations. earliest start of next bit e clock target mcu host drive to bkgd pin bkgd pin perceived start of bit time 10 cycles 10 cycles host samples bkgd pin target mcu drive and speedup pulse speedup pulse high impedance
background debug mode (bdm) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 293 18.3.3 bdm commands all bdm command opcodes are eight bits long and can be followed by an address and/or data, as indicated by the instruction. these commands do not require the cpu to be in active bdm for execution. the host controller must wait 150 cycles for a non- intrusive bdm command to execute before another command can be sent. this delay includes 128 cycles for the maximum delay for a dead cycle. for data read commands, the host must insert this delay between sending the address and attempting to read the data. bdm logic retains control of the internal buses unti l a read or write is completed. if an operation can be completed in a single cycle, it does not intrude on normal cpu operation. however, if an operation requires multiple cycles, cpu clocks ar e frozen until the operation is complete. the two types of bdm commands are: hardware firmware hardware commands allow target system memory to be read or written. target system memory includes all memory that is accessible by the cpu12 incl uding on-chip ram, eeprom, on-chip i/o and control registers, and external memory connected to the target hc12 mcu. hardware commands are implemented in hardware logic and do not require the hc12 mcu to be in bdm mode for execution. the control logic watches the cpu12 buses to find a fr ee bus cycle to execute the command so that the background access does not disturb the running applic ation programs. if a free cycle is not found within 128 e-clock cycles, the cpu12 is momentaril y frozen so the control logic can steal a cycle. refer to table 18-2 for commands implemented in bdm control logic. table 18-2. bdm hardware commands command opcode (hex) data description background 90 none enter background mode (if firmware enabled). read_bd_byte e4 16-bit address 16-bit data out read from memory with bdm in map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. status (1) e4 ff01, 0000 0000 (out) read_bd_byte $ff01. r unning user code. (bgnd instruction is not allowed.) ff01, 1000 0000 (out) read_bd_byte $ff01. bgnd instruction is allowed. ff01, 1100 0000 (out) read_bd_byte $ff01. background mode active (waiting for single wire serial command). read_bd_word ec 16-bit address 16-bit data out read from memory with bdm in map (may steal cycles if external access) must be aligned access. read_byte e0 16-bit address 16-bit data out read from memory with bdm out of map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. read_word e8 16-bit address 16-bit data out read from memory with bdm out of map (may steal cycles if external access) must be aligned access. write_bd_byte c4 16-bit address 16-bit data in write to memory with bdm in ma p (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. enable_ firmware (2) c4 ff01, 1xxx xxxx (in) write byte $ff01, set the enbdm bit. this allows execution of commands which are implemented in firmware. typically, read status, or in the msb, write the result back to status.
development support m68hc12b family data sheet, rev. 9.1 294 freescale semiconductor the second type of bdm commands are called firmwa re commands because they are implemented in a small rom within the hc12 mcu. the cpu must be in background mode to execute firmware commands. the usual way to get to background mode is by the hardware command background. the bdm rom is located at $ff20 to $ffff while bdm is active. there are also seven bytes of bdm registers which are located at $ff00 to $ff06 whil e bdm is active. the cpu executes code from this rom to perform the requested operation. the bdm firmware watches for serial commands and executes them as they are received. the firmware commands are shown in table 18-3 . each of the hardware and firmware bdm commands starts with an 8-bit command code (opcode). depending upon the commands, a 16-bit address and/or a 16 -bit data word is required as indicated in the tables by the command. all the read commands output 16 bits of data despite the byte/word implication in the command name. write_bd_word cc 16-bit address 16-bit data in write to memory with bdm in ma p (may steal cycles if external access) must be aligned access. write_byte c0 16-bit address 16-bit data in write to memory with bdm ou t of map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte. write_word c8 16-bit address 16-bit data in write to memory with bdm ou t of map (may steal cycles if external access) must be aligned access. 1. status command is a specific case of the read_bd_byte command. 2. enable_firmware is a specific case of the write_bd_byte command. table 18-3. bdm firmware commands command opcode (hex) data description read_next 62 16-bit data out x = x + 2; read next word pointed to by x read_pc 63 16-bit data out read program counter read_d 64 16-bit data out read d accumulator read_x 65 16-bit data out read x index register read_y 66 16-bit data out read y index register read_sp 67 16-bit data out read stack pointer write_next 42 16-bit data in x = x + 2; write next word pointed to by x write_pc 43 16-bit data in write program counter write_d 44 16-bit data in write d accumulator write_x 45 16-bit data in write x index register write_y 46 16-bit data in write y index register write_sp 47 16-bit data in write stack pointer go 08 none go to user program trace1 10 none execute one user instruction then return to bdm tag g o 1 8 n o n e enable tagging and go to user program table 18-2. bdm hardware commands (continued) command opcode (hex) data description
background debug mode (bdm) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 295 the external host should wait 150 e-clock cycles for a non-intrusive bdm command to execute before another command is sent. this delay includes 128 e-clock cycles for th e maximum delay for a free cycle. for data read commands, the host must insert this delay between sending the address and attempting to read the data. in the case of a write command, the host must delay after the data portion, before sending a new command, to be sure the write has finished. the external host should delay about 32 target e-clock cycles between a firmware read command and the data portion of these commands. this allows the bd m firmware to execute the instructions needed to get the requested data into the bdm shifter register. the external host should delay about 32 target e-clock cycles after the data portion of firmware write commands to allow bdm firmware to complete the requested write operation before a new serial command disturbs the bdm shifter register. the external host should delay about 64 target e-cl ock cycles after a trace1 or go command before starting any new serial command. this delay is needed because the bdm shifter register is used as a temporary data holding register during the exit sequence to user code. bdm logic retains control of the internal buses until a read or write is completed. if an operation can be completed in a single cycle, it does not intrude on normal cpu12 operation. however, if an operation requires multiple cycles, cpu12 clocks are frozen until the operation is complete. 18.3.4 bdm registers seven bdm registers are mapped into the standar d 64-kbyte address space when bdm is active. mapping is shown in table 18-4 . the content of the instruction register is deter mined by the type of backg round command being executed. the status register indicates bdm operating conditions. the shift register contains data being received or transmitted via the serial interface. the address register is temporary storage for bdm commands. the ccr holding register preserves the content of the cp u12 condition code register while bdm is active. the only registers of interest to users are the status register and the ccr holding register. the other bdm registers are used only by the bd m firmware to execute commands. the registers are accessed by means of the hardware read_bd and write_bd commands, but should not be written during bdm operation (except the ccrsav register which co uld be written to modify the ccr value). the instruction register is written by the bdm hardware as a result of serial data shifted in on the bkgd pin. it is readable and writable in special peripheral m ode on the parallel bus. it is discussed here for two conditions: when a hardware command is executed and when a firmware command is executed. the instruction register can be read or written in all modes. the hardware clears the instruction register if 512 e-clock cycles occur between falling edges from the host. table 18-4. bdm registers address register mnemonic $ff00 bdm instruction register instruction $ff01 bdm status register status $ff02?$ff03 bdm shift register shifter $ff04?$ff05 bdm address register address $ff06 bdm ccr holding register ccrsav
development support m68hc12b family data sheet, rev. 9.1 296 freescale semiconductor 18.3.5 bdm inst ruction register this section describes the bdm instruction register under hardware command and firmware command. 18.3.5.1 hardware command the bits in the bdm instruction regi ster have the following meanings when a hardware command is executed. h/f ? hardware/firmware flag 0 = firmware instruction 1 = hardware instruction data ? data flag 0 = no data 1 = data included in command r/w ? read/write flag 0 = write 1 = read bkgnd ? hardware request to enter active background mode 0 = not a hardware background command 1 = hardware background command (instruction = $90) w/b ? word/byte tansfer flag 0 = byte transfer 1 = word transfer bd/u ? bdm map/user map flag indicates whether bdm registers and rom are mapped to addresses $ff00 to $ffff in the standard 64-kbyte address space. used only by hardware read/write commands. 0 = bdm resources not in map 1 = bdm resources in map address: $ff00 bit 7654321bit 0 read: h/f data r/w bkgnd w/b bd/u 0 0 write: reset:00000000 figure 18-4. bdm instruction register (instruction)
background debug mode (bdm) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 297 18.3.5.2 firmware command the bits in the bdm instruction r egister have these meanings when a firmware command is executed. h/f ? hardware/firmware flag 0 = firmware control logic 1 = hardware control logic data ? data flag 0 = no data 1 = data included in command r/w ? read/write flag 0 = write 1 = read ttago ? trace, tag, go field regn ? register/next field indicates which register is being affected by a command. in the case of a read_next or write_next command, index register x is pre-in cremented by two and the word pointed to by x is then read or written. address: $ff00 bit 7654321bit 0 read: h/f data r/w ttago regn write: reset:00000000 figure 18-5. bdm instruction register (instruction) table 18-5. ttago decoding ttago value instruction 00 ? 01 go 10 trace1 11 taggo table 18-6. regn decoding ttago value instruction 000 ? 001 ? 010 read/write next 011 pc
development support m68hc12b family data sheet, rev. 9.1 298 freescale semiconductor 18.3.6 bdm status register this register can be read or wri tten by bdm commands or firmware. enbdm ? enable bdm bit (permit active background debug mode) 0 = bdm cannot be made active (hardware commands still allowed). 1 = bdm can be made active to allow firmware commands. bdmact ? background mode active status bit 0 = bdm not active 1 = bdm active and waiting for serial commands entag ? instruction tagging enable bit set by the taggo instruction and cleared when bdm is entered. 0 = tagging not enabled, or bdm active 1 = tagging active (bdm cannot process se rial commands while tagging is active.) sdv ? shifter data valid bit shows that valid data is in the serial interface shift register. used by firmware-based instructions. 0 = no valid data 1 = valid data trace asserted by the trace1 instruction 18.3.7 bdm shifter register the 16-bit shifter register contains data being receiv ed or transmitted via the serial interface. it is also used by the bdm firmware for temporary storage. the register can be read or written in all modes but is not normally accessed by users. address: $ff01 bit 7654321bit 0 read: enbdm edmact entag sdv trace 0 0 0 write: reset:00000000 single-chip peripheral:10000000 figure 18-6. bdm status register (status) address: $ff02 bit 7654321bit 0 read: s15 s14 s13 s12 s11 s10 s9 s8 write: reset:00000000 address: $ff03 bit 7654321bit 0 read: s7 s6 s5 s4 s3 s2 s1 s0 write: reset:00000000 figure 18-7. bdm shifter register (shifter)
breakpoints m68hc12b family data sheet, rev. 9.1 freescale semiconductor 299 18.3.8 bdm address register the 16-bit address register is temporary storage for bdm hardware and firmware commands. the register can be read in all modes but is not norma lly accessed by users. it is written only by bdm hardware. 18.3.9 bdm ccr holding register the ccrsav register is used to save the state of t he condition code register (ccr) of the user?s program when entering bdm. it is also used for temporary stor age in the bdm firmware. the register is initialized by the firmware to equ al the cpu ccr register. 18.4 breakpoints hardware breakpoints are used to debug software on the mcu by comparing actual address and data values to predetermined data in setup registers. a successful comparison places the cpu in background debug mode (bdm) or initiates a software interrupt (swi). breakpoint features designed into the mcu include: mode selection for bdm or swi generation program fetch tagging for cycle of execution breakpoint second address compare in dual address modes range compare by disable of low byte address data compare in full feature mode for non-tagged breakpoint byte masking for high/low byte data compares r/w compare for non-tagged compares tag inhibit on bdm trace address: $ff04 bit 7654321bit 0 read: a15 a14 a13 a12 a11 a10 a9 a8 write: reset:00000000 address: $ff05 bit 7654321bit 0 read: a7 a6 a5 a4 a3 a2 a1 a0 write: reset:00000000 figure 18-8. bdm address register (address) address: $ff06 bit 7654321bit 0 read: ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 write: reset:00000000 figure 18-9. bdm ccr holding register (ccrsav)
development support m68hc12b family data sheet, rev. 9.1 300 freescale semiconductor 18.4.1 breakpoint modes three modes of operation determine the type of breakpoint in effect. 1. dual address-only breakpoints, each of which causes a software interrupt (swi) 2. single full-feature breakpoint which causes the part to enter background debug mode (bdm) 3. dual address-only breakpoints, each of which causes the part to enter bdm breakpoints do not occur when bdm is active. 18.4.1.1 swi dual address mode in this mode, dual address-only breakpoints can be se t, each of which causes a software interrupt. this is the only breakpoint mode which can force the cpu to execute an swi. program fetch tagging is the default in this mode; data breakpoints are not possi ble. in dual mode each addre ss breakpoint is affected by the respective bkale bit. the bkxrw, bkxrwe , bkmbh, and bkmbl bits are ignored. in dual address mode, the bkdbe becomes an enable for the second address breakpoint. 18.4.1.2 bdm full breakpoint mode this is a single full-featured breakpoint which c auses the part to enter background debug mode. bk1ale, bk1rw, and bk1rwe have no meani ng in full breakpoint mode. bkdbe enables data compare but has no meaning if bkpm = 1. bkmbh and bkmbl allow masking of high and low byte compares but has no meaning if bkpm = 1. bk0ale enables compare of low address byte. breakpoints are not allowed if the bdm mode is already active. active mode means the cpu is executing out of the bdm rom. bdm should not be entered from a breakpoint unless the enable bit is set in the bdm. this is important because even if the enable bit in the bdm is negated, the cpu actually does execute the bdm rom code. it checks the enable and returns if not set. if the bdm is not serviced by the monitor, then the breakpoint would be re-asserted when the bdm returns to normal cpu flow. there is no hardware to enforce restriction of breakpoint operation if the bdm is not enabled. 18.4.1.3 bdm dual address mode this mode has dual address-only br eakpoints, each of which causes the part to enter background debug mode. in dual mode, each address breakpoint is affected by the bkpm bit, the bkxale bits, and the bkxrw and bkxrwe bits. in dual address mode, the bkdbe becomes an enable for the second address breakpoint. the bkmbh and bkmbl bits have no effect when in a dual address mode. bdm may be entered by a breakpoint only if an internal signal from the bdm indicates background debug mode is enabled. if bkpm = 1, then bkxrw, bkxrw e, bkmbh, and bkmbl have no meaning. breakpoints are not allowed if the bdm is already active. active mode means the cpu is executing out of the bdm rom. bdm should not be entered from a breakpoint unless the enable bit is set in the bdm. this is important because even if the enable bit in the bdm is negated, the cpu actually does execute the bdm rom code. it checks the enable and returns if not set. if the bdm is not serviced by the monitor, then the breakpoint would be re-asserted when the bdm returns to normal cpu flow. there is no hardware to enforce restriction of breakpoint operation if the bdm is not enabled.
breakpoints m68hc12b family data sheet, rev. 9.1 freescale semiconductor 301 18.4.2 breakpoint registers breakpoint operation consists of co mparing data in the breakpoint addr ess registers (brkah/brkal) to the address bus and comparing data in the breakpoint data registers (brkdh/brkdl) to the data bus. the breakpoint data registers also can be compared to the address bus. the scope of comparison can be expanded by ignoring the least significa nt byte of address or data matches. the scope of comparison can be limited to program dat a only by setting the bkpm bit in breakpoint control register 0. to trace program flow, setting the bkpm bit causes address comparison of program data only. control bits are also available that a llow checking read/write matches. 18.4.2.1 breakpoint control register 0 read and write anytime. this register is used to control the breakpoint logic. bken1 and bken0 ? breakpoint mode enable bits see table 18-7 . bkpm ? break on program addresses this bit controls whether the breakpoint causes an immediate data breakpoint (next instruction boundary) or a delayed program breakpoint relat ed to an executable opcode. data and unexecuted opcodes cannot cause a break if this bit is set. this bit has no meaning in swi dual address mode. the swi mode only performs program breakpoints. 0 = on match, break at the next instruction boundary 1 = on match, break if the match is an instruction to be executed. this uses tagging as its breakpoint mechanism. bk1ale ? breakpoint 1 range control bit only valid in dual address mode 0 = brkdl is not used to compare to the address bus. 1 = brkdl is used to compare to the address bus. address: $0020 bit 7654321bit 0 read: bken1 bken0 bkpm 0 bk1ale bk0ale 0 0 write: reset:00000000 figure 18-10. breakpoint control register 0 (brkct0) table 18-7. breakpoint mode control bken1 bken0 mode selected brkah/l usage brkdh/l usage r/w range 0 0 breakpoints off ? ? ? ? 0 1 swi ? dual address mode address match address match no yes 1 0 bdm ? full breakpoint mode address match data match yes yes 1 1 bdm ? dual address mode address match address match yes yes
development support m68hc12b family data sheet, rev. 9.1 302 freescale semiconductor bk0ale ? breakpoint 0 range control bit valid in all modes 0 = brkal is not used to compare to the address bus. 1 = brkal is used to compare to the address bus. 18.4.2.2 breakpoint control register 1 this register is read/write in all modes. bkdbe ? enable data bus bit enables comparing of address or data bus values using the brkdh/l registers. 0 = brkdh/l registers are not used in any comparison. 1 = brkdh/l registers are used to compare address or data (depending upon the mode selections bken1 and bken0). bkmbh ? breakpoint mask high bit disables the comparing of the high byte of data w hen in full breakpoint mode. used in conjunction with the bkdbe bit (which should be set) 0 = high byte of data bus (bits 15:8) are compared to brkdh. 1 = high byte is not used in comparisons. bkmbl ? breakpoint mask low bit disables the matching of the low byte of data when in full breakpoint mode. used in conjunction with the bkdbe bit (which should be set) 0 = low byte of data bus (bits 7?0) are compared to brkdl. 1 = low byte is not used to in comparisons. bk1rwe ? r/w compare enable bit enables the comparison of the r/w signal to further specify what causes a match. this bit is not useful in program breakpoints or in full breakpoint mode. this bit is used in conjunction with a second address in dual address mode when bkdbe = 1. 0 = r/w is not used in comparisons. 1 = r/w is used in comparisons. table 18-8. breakpoint address range control bk1ale bk0ale address range selected ? 0 upper 8-bit address only for full mode or dual mode bkp0 ? 1 full 16-bit address for full mode or dual mode bkp0 0 ? upper 8-bit address only for dual mode bkp1 1 ? full 16-bit address for dual mode bkp1 address: $0021 bit 7654321bit 0 read: 0 bkdbe bkmbh bkmbl bk1rwe bk1rw bk0rwe bk0rw write: reset:00000000 figure 18-11. breakpoint control register 1 (brkct1)
breakpoints m68hc12b family data sheet, rev. 9.1 freescale semiconductor 303 bk1rw ? r/w compare value bit when bk1rwe = 1, this bit determines the type of bus cycle to match. 0 = a write cycle is matched. 1 = a read cycle is matched. bk0rwe ? r/w compare enable bit enables the comparison of the r/w signal to further specify what causes a match. this bit is not useful in program breakpoints. 0 = r/w is not used in the comparisons. 1 = r/w is used in comparisons. bk0rw ? r/w compare value bit when bk0rwe = 1, this bit determines the type of bus cycle to match. 0 = write cycle is matched. 1 = read cycle is matched. 18.4.2.3 breakpoint address register high these bits are used to compare against the most significant byte of the address bus. 18.4.2.4 breakpoint address register low these bits are used to compare against the least signi ficant byte of the address bus. these bits may be excluded from being used in the match if bk0ale = 0. table 18-9. breakpoint read/write control bk1rwe bk1rw bk0rwe bk0rw read/write selected ?? 0 xr/w is don?t care for full mode or dual mode bkp0 ?? 1 0r/w is write for full mode or dual mode bkp0 ?? 1 1r/w is read for full mode or dual mode bkp0 0x??r/w is don?t care for dual mode bkp1 10??r/w is write for dual mode bkp1 11??r/w is read for dual mode bkp1 address: $0022 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: power on reset:00000000 figure 18-12. breakpoint address register high (brkah) address: $0023 bit 7654321bit 0 read: bit 7654321bit 0 write: power on reset:00000000 figure 18-13. breakpoint address register low (brkal)
development support m68hc12b family data sheet, rev. 9.1 304 freescale semiconductor 18.4.2.5 breakpoint data register high these bits are compared to the most significant byte of the data bus in full breakpoint mode or the most significant byte of the address bus in dual a ddress modes. bke1, bke0, bkdbe, and bkmbh control how this byte is used in the breakpoint comparison. 18.4.2.6 breakpoint data register low byte these bits are compared to the least significant byte of the data bus in full breakpoint mode or the least significant byte of the address bus in dual address modes. bken1, bken0, bkdbe, bk1ale, and bkmbl control how this byte is used in the breakpoint comparison. note after a power-on reset, registers brkah, brkal, brkdh, and brkdl are cleared but these registers are not affected by normal resets. 18.5 instruction tagging the instruction queue and cycle-by-cycle cpu activity can be reconstructed in real time or from trace history that was captured by a logic analyzer. however, the reconstructed queue cannot be used to stop the cpu at a specific instruction, because execution has already begun by the time an operation is visible outside the mcu. a separate instruction tagging mechanism is provided for this purpose. executing the bdm taggo command configures two mcu pins for tagging. tagging information is latched on the falling edge of eclk along with program information as it is fetched. tagging is allowed in all modes. tagging is disabled when bdm becomes active and bdm serial commands cannot be processed while tagging is active. taghi is a shared function of the bkgd pin. taglo is a shared function of the pe3/lstrb pin, a multiplexed i/o pin. for 1/4 cycle before and after the rising edge of the e clock, this pin is the lstrb driven output. taglo and taghi inputs are captured at the falling edge of the e clock. a logic 0 on taghi and/or taglo marks (tags) the instruction on the high and/or low byte of the program word that was on the data bus at the same falling edge of the e clock. address: $0024 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: power on reset:00000000 figure 18-14. breakpoint data register high (brkdh) address: $0025 bit 7654321bit 0 read: bit 7654321bit 0 write: power on reset:00000000 figure 18-15. breakpoint data register low (brkdl)
instruction tagging m68hc12b family data sheet, rev. 9.1 freescale semiconductor 305 table 18-10 shows the functions of the two tagging pins. the pins operate independently; the state of one pin does not affect the function of the other. the presen ce of logic level 0 on either pin at the fall of eclk performs the indicated function. tagging is allowed in all modes. ta gging is disabled when bdm becomes active and bdm serial commands are not processed while tagging is active. the tag follows the information in the queue as the queue is advanced. when a tagged instruction reaches the head of the queue, the cpu enters active background debug mode rather than executing the instruction. this is the mechanism by which a development system initiates hardware breakpoints. currently, the tool configuration shown in figure 18-16 is used. figure 18-16. bdm tool connector table 18-10. tag pin function taghi taglo tag 1 1 no tag 10 low byte 0 1 high byte 0 0 both bytes 2 4 6 5 3 1 reset bkgd v dd gnd v fp nc
development support m68hc12b family data sheet, rev. 9.1 306 freescale semiconductor
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 307 chapter 19 electrical specifications 19.1 introduction this section contains electrical and timing specifications. 19.2 maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 19.5 5.0 volt dc electrical characteristics for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). rating symbol value unit supply voltage v dd , v dda , v ddx ?0.3 to +6.5 v input voltage v in ?0.3 to +6.5 v maximum current per pin excluding v dd and v ss i in 25 ma storage temperature t stg ?55 to +150 c v dd differential voltage v dd ?v ddx 6.5 v
electrical specifications m68hc12b family data sheet, rev. 9.1 308 freescale semiconductor 19.3 functional operating range 19.4 thermal characteristics rating symbol value unit all devices in this document meet these operating temperature ranges: ?c? temperature range ?v? temperature range ?m? temperature range t a t l to t h ? 40 to + 85 ? 40 to + 105 ? 40 to + 125 c operating voltage range v dd 5.0 10% v characteristic symbol value unit average junction temperature t j t a + (p d ja ) c ambient temperature t a user-determined c package thermal resistance (junction-to-ambient) 80-pin quad flat pack (qfp) ja 76 c/w total power dissipation (1) 1. this is an approximate value, neglecting p i/o . p d p int + p i/o or w device internal power dissipation p int i dd v dd w i/o pin power dissipation (2) 2. for most applications, p i/o ? p int and can be neglected. p i/o user-determined w a constant (3) 3. k is a constant pertaining to the device. solve for k with a known t a and a measured p d (at equilibrium). use this value of k to solve for p d and t j iteratively for any value of t a . k p d (t a + 273 c) + ja p d 2 w/ c k t j 273 c + -------------------------- -
5.0 volt dc electrica l characteristics m68hc12b family data sheet, rev. 9.1 freescale semiconductor 309 19.5 5.0 volt dc elec trical characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min max unit input high voltage, all inputs v ih 0.7 v dd v dd + 0.3 v input low voltage, all inputs v il v ss ? 0.3 0.2 v dd v output high voltage, all i/o and output pins except xtal normal drive strength i oh = ? 10.0 a i oh = ? 0.8 ma reduced drive strength i oh = ? 4.0 a i oh = ? 0.3 ma v oh v dd ? 0.2 v dd ? 0.8 v dd ? 0.2 v dd ? 0.8 ? ? ? ? v output low voltage, all i/o and output pins except xtal normal drive strength i ol = 10.0 a i ol = 1.6 ma reduced drive strength i ol = 3.6 a i ol = 0.6 ma v ol ? ? ? ? v ss + 0.2 v ss + 0.4 v ss + 0.2 v ss + 0.4 v input leakage current (2) v in = v dd or v ss all input-only pins except atd (3) and v fp 2. specification is for parts in the ?40 to +85 c range. higher temperature ranges will result in increased current leakage. 3. see 19.8 atd dc electrical characteristics . i in ? 5 a three-state leakage, i/o ports, bkgd, and reset i oz ? 2.5 a input capacitance all input pins and atd pins (non-sampling) atd pins (sampling) all i/o pins c in ? ? ? 10 15 20 pf output load capacitance all outputs except ps7?ps4 ps7?ps4 when configured as spi c l ? ? 90 200 pf programmable active pullup current xirq , dbe , lstrb , r/w , ports a, b, dlc, p, s, t moda, modb active pulldown during reset bkgd passive pullup i apu 50 50 50 500 500 500 a
electrical specifications m68hc12b family data sheet, rev. 9.1 310 freescale semiconductor 19.6 supply current 19.7 atd maximum ratings characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol 2 mhz4 mhz8 mhz unit maximum total supply current run: single-chip mode expanded mode i dd 15 25 25 45 45 70 ma ma wait: (all peripheral functions shut down) single-chip mode expanded mode w idd 1.5 4 3 7 5 10 ma ma stop: single-chip mode, no clocks ? 40 to + 85 + 85 to + 105 + 105 to + 125 s idd 10 25 50 10 25 50 10 25 50 a a a maximum power dissipation (2) single-chip mode expanded mode 2. includes i dd and i dda p d 75 125 125 225 225 350 mw characteristic symbol value units atd reference voltage v rh v dda v rl v ssa v rh v rl ? 0.3 to + 6.5 ? 0.3 to + 6.5 v v ss differential voltage | v ss ? v ssa | 0.1 v v dd differential voltage v dd ? v dda v dda ? v dd 6.5 0.3 v v ref differential voltage | v rh ? v rl | 6.5 v reference to supply differential voltage | v rh ? v dda | 6.5 v
atd dc electrical characteristics m68hc12b family data sheet, rev. 9.1 freescale semiconductor 311 19.8 atd dc electrical characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , atd clock = 2 mhz, unless otherwise noted symbol min max unit analog supply voltage v dda 4.5 5.5 v analog supply current, normal operation i dda ?1.0ma reference voltage, low v rl v ssa v dda / 2 v reference voltage, high v rh v dda / 2v dda v v ref differential reference voltage (2) 2. accuracy is guaranteed at v rh ? v rl = 5.0 v 10%. v rh ? v rl 4.5 5.5 v input voltage (3) 3. to obtain full-scale, full-range results, v ssa v rl v indc v rh v dda . v indc v ssa v dda v input current, off channel (4) 4. maximum leakage occurs at maximum operating temperature. cu rrent decreases by approximately one-half for each 10 c decrease from maximum temperature. i off ? 100 na reference supply current i ref ? 250 a input capacitancenot sampling sampling c inn c ins ? ? 10 15 pf
electrical specifications m68hc12b family data sheet, rev. 9.1 312 freescale semiconductor 19.9 analog converter operating characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , atd clock = 2 mhz, unless otherwise noted symbol min typ max unit 8-bit resolution (2) 2. v rh ? v rl 5.12 v; v dda ? v ssa = 5.12 v 1 count ? 20 ? mv 8-bit differential non-linearity (3) 3. at v ref = 5.12 v, one 8-bit count = 20 mv, and one 10-bit count = 5 mv. inl and dnl are characterized using the process window parameters affecting the atd accuracy, but they are not tested. dnl ? 0.5 ? + 0.5 count 8-bit integral non-linearity (3) inl ? 1? + 1 count 8-bit absolute error (3), (4) 2, 4, 8, and 16 atd sample clocks 4. eight-bit absolute error of 1 count (20 mv) includes 1/2 count (10 mv) inhe rent quantization error and 1/2 count (10 mv) circuit (differential, integral, and offset) error. ae ? 1? + 1 count 10-bit resolution (2) 1 count ? 5 ? mv 10-bit differential non-linearity (3) dnl ?2 ? 2 count 10-bit integral non-linearity (3) inl ?2 ? 2 count 10-bit absolute error (3) 2, 4, 8, and 16 atd sample clocks ae ?2.5 ? 2.5 count maximum source impedance r s ?20 see (5) 5. maximum source impedance is application-dependent. error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. error from junction leakage is a function of external source impedance and input leakage current. expected error in result value due to junction leakage is expressed in voltage (v errj ): v errj = r s i off where i off is a function of operating temperature. charge-sharing e ffects with internal capacitors are a function of atd clock speed, the number of channels being scanned, and source im pedance. for 8-bit conversions, charge pump leakage is computed as: v errj = 0.25 pf v dda r s atdclk/(8 number of channels) k ?
atd ac operating charac teristics (operating) m68hc12b family data sheet, rev. 9.1 freescale semiconductor 313 19.10 atd ac operating characteristics (operating) 19.11 eeprom characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , atd clock = 2 mhz, unless otherwise noted symbol min max unit mcu clock frequency (p-clock) f pclk 2.0 8.0 mhz atd operating clock frequency f at d c l k 0.5 2.0 mhz atd 8-bit conversion period atd clock cycles (2) atd conversion time (3) 2. the minimum time assumes a final sample period of 2 atd clock cycles wh ile the maximum time assumes a final sample period of 16 atd clocks. 3. this assumes an atd clock frequency of 2.0 mhz. n conv8 t conv8 18 9 32 16 cycles s atd 10-bit conversion period atd clock cycles (2) atd conversion time (3) n conv10 t conv10 20 10.0 34 17 cycles s stop and atd power-up recovery time (4) v dda = 5.0 v 4. from the time adpu is asserted until the time an atd conversion can begin t sr ?10 s characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min typ max unit minimum programming clock frequency (2) 2. rc oscillator must be enabled if programming is desired and f sys < f prog . f prog 1.0 ? ? mhz programming time t prog 10.0 ? 10.5 ms clock recovery time, following stop, to continue programming t crstop ?? t prog + 1 ms erase time t erase 10.0 ? 10.5 ms write/erase endurance ? 10,000 ? ? cycles data retention ? 10 ? ? years
electrical specifications m68hc12b family data sheet, rev. 9.1 314 freescale semiconductor 19.12 flash eeprom characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min typ max units program/erase supply voltage read only program/erase/verify v fp v dd ? 0.35 11.4 v dd 12.0 v dd + 0.5 12.6 v program/erase supply current word program (v fp = 12 v) erase (v fp = 12 v) i fp ??30 4 ma number of programming pulses n pp ? ? 50 pulses programming pulse t ppulse 20 ? 25 s program to verify time t vprog 10 ? ? s program margin p m 100 (2) 2. the number of margin pulses required is the same as the number of pulses used to program or erase. ??% number of erase pulses n ep ? ? 5 pulses erase pulse t epulse 5?10ms erase to verify time t verase 1??ms erase margin e m 100 (3) ??% program/erase endurance 100 ? ? cycles data retention 10 ? ? years
flash eeprom characteristics m68hc12b family data sheet, rev. 9.1 freescale semiconductor 315 19.12.1 programming voltage supply envelope the key to preventing damage to the flash array or corruption of the data contained in the memory is the programming voltage envelope shown in figure 19-1 . many of the problems that customers experience with flash devices are due to a failure to ensure that their voltage sources always meet these requirements. the most important single thing to remember from this diagram is that v fp and v dd should always be at the same level, except during an actual program or erase cycle. corruption of flash data is often encountered when v fp is allowed to exceed v dd during the power-up and power-down phases. conversely, if v fp is allowed to fall below 0.35 volts lower than v dd at any time, damage to the flash array can occur. note although figure 19-1 shows a lower boundary of 4.15 volts on v fp during the normal read phase, v fp always must be no more than .35 volts below v dd . for example, if the operating voltage of v dd in the system is 5.2 volts, v fp can be no lower than 4.85 volts. figure 19-1. programming voltage envelope 13.5 v 12.6 v 11.4 v 5.5 v 4.5 v 4.15 v 0 v ?0.30 v v fp envelope v dd envelope combined v dd and v fp 30 ns maximum t er program erase power down power up normal read
electrical specifications m68hc12b family data sheet, rev. 9.1 316 freescale semiconductor 19.12.2 example v fp protection circuitry figure 19-2 shows an example of a circuit which, if pro perly implemented, can maintain the appropriate voltage levels on the v fp pin. this section outlines the design fo r this circuit, what each component is intended to do, and some design considerations when designing v fp pin protection. figure 19-2. v fp supply circuit the general idea of this circuit implementation is to supply v fp from a dc-dc converter. this dc-dc converter, like most, provides a s hutdown feature which allows the conv erter?s output to be shut off. when the shdn pin on the converter is pulled high, as the 10-k ? pullup resistor (r1) does, the output v out is shorted to the v dd supply. this requires that the programmi ng and erasing routines assert a port pin on the mcu to turn on the converter and supply the 12-volt programming voltage during the programming or erasing cycle. simple programming a nd erasing routines, such as those shown earlier in this application note, will no longer suffice. by implementing this solution, v fp is tied to v dd on power-up and power-down, ensuring that they rise and fall together. capacitors c5 and c6 are the normal decoupling capacitors on the v dd supply lines. c3 is used to reduce electromagnetic interference (emi) in the circuit. if c3 is too large, v fp will not be allowed to fall with v dd , potentially causing data corruption in the flash array. (refer to figure 19-3 .) c4 is where the dc-dc converter stores charge to supply v out to the target device. the supply must be able to source approximately 30 ma of current for at least 20 s (based on programming cycle requirements) and 4 ma of current for at least 10 ms (based on erase cycle requirements). a certain degree of experimentation might be required when selecting c4 and c3. when trying different capacitor values, always monitor the effects on v fp decay during power-down and current supplied to the v fp pin. r1 must be no larger than 10 k ? , to make certain that the shdn pin on the dc-dc converter is never allowed to fall below v dd unless the output pin of the microcontroller is driven low. the external pullup ensures this behavior, no matter what port pin is used on the microcontroller or what the internal structure of that pin looks like. without a strong enough pullu p resistor on r1, the voltage on the shdn pin might drop during a reset event, causing the dc-dc converter to activate and begin driving the voltage on v out to begin to rise to 12 volts. this would result in data corruption in the flash. v dd c1+ c1 ? c2+ c2? 5 2 1 4 3 220 nf 220 nf 7 gnd shdn v out st662a 6 8 c4 10 f c3 1?100 nf r1 10 k ? v fp shutdown c5 10 f c6 100 nf v dd v fp i/o v ss v dd
flash eeprom characteristics m68hc12b family data sheet, rev. 9.1 freescale semiconductor 317 note figure 19-2 is different from the recommended circuit shown in information about st662a from st microelectronics , but it is correct. the change is in the location of the capacitor c4, which is now placed between v dd and v fp . this change was implemented with the cooperation of st microelectronics to aid in tracking a rapidly falling v dd voltage level, such as in figure 19-3 and figure 19-4 . this circuit also has been verified with the maxim integrated products device (max662). be certain that v fp decays with v dd , as shown in figure 19-4 , as new capacitance values are tested. the rate of decay of the v dd supply powering down will help define how large the c3 capacitance can be made. figure 19-3. v fp exceeding v dd during power-down
electrical specifications m68hc12b family data sheet, rev. 9.1 318 freescale semiconductor figure 19-4. v fp tracking v dd during power-down when checking to ensure that the reservoir capacitance value of c4 is not too low, the voltage level of v fp can be monitored during an initial erase and a write pulse. remember that the largest current draw on erasing is when all of the bits of the fl ash are programmed to 0. conversely, the highest programming current is seen when pr ogramming all the bits to 0 from the erased state of 1. the user should look at this on an os cilloscope, due to the brevity of the puls es. using a port pin or the shdn signal may be useful to trigger the scope when the pulses are fired. if the voltage dips below 11.4 volts, the capacitance used can be increased, but be su re to verify that decay rates of v dd and v fp are still the same. if v fp is declining with each successive pulse, try inserting some delays between each pulse to allow the charge pump to recharge. the solution shown here uses the st662a dc-dc converter, but any similar device will work. some other options are the ltc1262c from linear technology corporation or the max662 from maxim integrated products, inc.
pulse-width modulato r characteristics m68hc12b family data sheet, rev. 9.1 freescale semiconductor 319 19.13 pulse-width modu lator characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min max unit e-clock frequency f eclk ?8.0mhz a-clock frequency selectable f aclk f eclk /128 f eclk hz b-clock frequency selectable f bclk f eclk /128 f eclk hz left-aligned pwm frequency 8-bit 16-bit f lpwm f eclk /1 m f eclk /256 m f eclk /2 f eclk /2 hz left-aligned pwm resolution r lpwm f eclk /4 k f eclk hz center-aligned pwm frequency 8-bit 16-bit f cpwm f eclk /2 m f eclk /512 m f eclk f eclk hz center-aligned pwm resolution r cpwm f eclk /4 k f eclk hz
electrical specifications m68hc12b family data sheet, rev. 9.1 320 freescale semiconductor 19.14 control timing figure 19-5. timer inputs characteristic symbol 8.0 mhz unit min max frequency of operation f o dc 8.0 mhz e-clock period t cyc 125 ? ns crystal frequency f xtal ? 16.0 mhz external oscillator frequency 2 f o dc 16.0 mhz processor control setup time t pcsu = t cyc / 2 + 20 t pcsu 82 ? ns reset input pulse width (1) to guarantee external reset vector minimum input time (can be pre-empted by internal reset) 1. reset is recognized during the first clock cycle it is held low. in ternal circuitry then drives the pin low for 16 clock cycles, releases the pin, and samp les the pin level eight cycl es later to determine the source of the interrupt. pw rstl 32 2 ? ? t cyc mode programming setup time t mps 4? t cyc mode programming hold time t mph 10 ? ns interrupt pulse width, irq edge-sensitive mode pw irq = 2 t cyc + 20 pw irq 270 ? ns wait recovery startup time t wrs = 4 t cyc t wrs ?4 t cyc timer input capture pulse width pw tim = 2 t cyc + 20 pw tim 270 ? ns pulse accumulator pulse width pw pa tbd ? ns pt7 2 pt7 1 pt7?pt0 (2) pt7?pt0 (1) n otes: 1. rising edge sensitive input 2. falling edge sensitive input pw tim pw pa
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 321 control timing figure 19-6. power-on and external reset timing diagram t pcsu internal moda, modb eclk extal v dd reset 4098 t cyc free fffe fffe 3rd 1st 2nd free fffe fffe fffe t mph pw rstl t mps address pipe pipe pipe 1st exec 3rd pipe 2nd pipe 1st pipe 1st exec note: reset timing is subject to change.
m68hc12b family data sheet, rev. 9.1 322 freescale semiconductor electrical specifications figure 19-7. stop recovery timing diagram pw irq t stopdelay (3) irq (1) irq (2) or xirq eclk 1st address (4) sp-9 free free vector free free resume program with instruction which follows the stop instruction. internal address (5) clocks notes: 1. edge-sensitive irq pin (irqe bit = 1) 2. level-sensitive irq pin (irqe bit = 0) 3. t stopdelay = 4098 t cyc if dly bit = 1 or 2 t cyc if dly = 0. 4. xirq with x bit in ccr = 1. 5. irq or (xirq with x bit in ccr = 0) opt 1st 2nd 3rd 1st exec pipe pipe exec sp-8 sp-6 fetch pipe sp-6 sp-8 sp-9
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 323 control timing figure 19-8. wait recovery timing diagram t pcsu pc, iy, ix, b:a, ccr stack registers eclk r/w address irq , xirq , or internal interrupts sp ? 2 sp ? 4 sp ? 6 . . . sp ? 9 sp ? 9 sp ? 9 . . . sp ? 9 sp ? 9 vector free 1st 2nd 3rd pipe t wrs note: reset also causes recovery from wait. address pipe pipe 1st exec
m68hc12b family data sheet, rev. 9.1 324 freescale semiconductor electrical specifications figure 19-9. interrupt timing diagram t pcsu pc, iy, ix, b:a, ccr stack registers eclk r/w address irq , xirq , or internal interrupts sp ? 2 sp ? 4 sp ? 6 . . . sp ? 9 sp ? 9 sp ? 9 . . . sp ? 9 sp ? 9 vector free 1st 2nd 3rd pipe t wrs note: reset also causes recovery from wait. address pipe pipe 1st exec
peripheral port timing m68hc12b family data sheet, rev. 9.1 freescale semiconductor 325 19.15 peripheral port timing figure 19-10. port read timing diagram figure 19-11. port write timing diagram characteristic symbol 8.0 mhz unit min max frequency of operation e-clock frequency f o dc 8.0 mhz e-clock period t cyc 125 ? ns peripheral data setup time mcu read of ports t pdsu = t cyc / 2 + 40 t pdsu 102 ? ns peripheral data hold time mcu read of ports t pdh 0?ns delay time, peripheral data write mcu write to ports t pwd ?40ns delay time, peripheral data write mcu write to port can t pwd ?71ns eclk mcu read of port ports t pdsu t pdh eclk mcu write to port previous port data new data valid port a t pwd
electrical specifications m68hc12b family data sheet, rev. 9.1 326 freescale semiconductor 19.16 multiplexed expansion bus timing note use of the multiplexed expansion bus at 8 mhz is discouraged due to tad delay factors. num characteristic (1), (2), (3), (4), (5) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted 2. all timings are calculated for normal port drives. 3. crystal input is required to be within 45% to 55% duty. 4. reduced drive must be off to meet these timings. 5. unequalled loading of pins will affect relative timing numbers. delay symbol 8 mhz 2 mhz unit min max min max ? frequency of operation (e-clock frequency) ? f o dc 8.0 dc 8.0 mhz 1 cycle timet cyc = 1 / f o ? t cyc 125 ? 500 ? ns 2 pulse width, e lowpw el = t cyc / 2 + delay ? 4 pw el 59 ? 246 ? ns 3 pulse width, e high (6) pw eh = t cyc / 2 + delay 6. this characteristic is affected by clock stretch. add n t cyc where n = 0, 1, 2, or 3, depending on the number of clock stretches. ? 2 pw eh 59 ? 248 ? ns 5 address delay timet ad = t cyc / 4 + delay 27 t ad ? 67.5 ? 152 ns 7 address valid time to eclk riset av = pw el ? t ad ? t av ?6.2 ? 94 ? ns 8 multiplexed address hold timet mah = t cyc / 4 + delay ? 18 t mah 13 ? 107 ? ns 9 address hold to data valid ? t ahds 30 ? 20 ? ns 10 data hold to high impedancet dhz = t ad ? 20 ? t dhz ? 45.2 ? 132 ns 11 read data setup time ? t dsr 31.2 ? 25 ? ns 12 read data hold time ? t dhr 0?0?ns 13 write data delay time ? t ddw ? 62.5 ? 165 ns 14 write data hold time ? t dhw 25 ? 20 ? ns 15 write data setup time (6) t dsw = pw eh ? t ddw ? t dsw 5.8 ? 83 ? ns 16 read/write delay timet rwd = t cyc / 4 + delay 18 t rwd ? 57.5 ? 143 ns 17 read/write valid time to e riset rwv = pw el ? t rwd ? t rwv 3.8 ? 103 ? ns 18 read/write hold time ? t rwh 25 ? 20 ? ns 19 low strobe (7) delay timet lsd = t cyc / 4 + delay 7. without tag enabled 18 t lsd ? 57.5 ? 143 ns 20 low strobe (7) valid time to e riset lsv = pw el ? t lsd ? t lsv 3.8 ? 103 ? ns 21 low strobe (7) hold time ? t lsh 25 ? 20 ? ns 22 address access time (6) t acca = t cyc ? t ad ? t dsr ? t acca ? 27.6 ? 323 ns 23 access time from e rise (6) t acce = pw eh ? t dsr ? t acce ? 27.8 ? 223 ns 24 dbe delay from eclk rise (6) t dbed = t cyc / 4 + delay 8 t dbed ? 57.5 ? 133 ns 25 dbe valid timet dbe = pw eh ? t dbed ? t dbe 11.8 ? 115 ? ns 26 dbe hold time from eclk fall ? t dbeh ?3 10 ?3 10 ns
multiplexed expansion bus timing m68hc12b family data sheet, rev. 9.1 freescale semiconductor 327 figure 19-12. multiplexed expansion bus timing diagram dbe 24 25 eclk r/w 1 2 3 18 11 12 14 note: measurement points shown are 20% and 70% of v dd . 13 16 17 read write 23 lstrb 21 19 20 w/o tag enabled 5 7 22 8 15 address/data multiplexed address address data data 10 9 26
electrical specifications m68hc12b family data sheet, rev. 9.1 328 freescale semiconductor 19.17 serial peripheral interface (spi) timing num function (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , 200 pf load on all spi pins, ac timing is shown with respect to 20% v dd and 70% v dd levels, unless otherwise noted. symbol min max unit operating frequency master slave f op dc dc 1 / 2 1 / 2 e-clock frequency 1 sck period master slave t sck 2 2 256 ? t cyc t cyc 2 enable lead time master slave t lead 1 / 2 1 ? ? t sck t cyc 3 enable lag time master slave t lag 1 / 2 1 ? ? t sck t cyc 4 clock (sck) high or low time master slave t wsck t cyc ? 30 t cyc ? 30 128 t cyc ? ns ns 5 sequential transfer delay master slave t td 1 / 2 1 ? ? t sck t cyc 6 data setup time (inputs) master slave t su 30 30 ? ? ns ns 7 data hold time (inputs) master slave t hi 0 30 ? ? ns ns 8 slave access time t a ?1 t cyc 9 slave miso disable time t dis ?1 t cyc 10 data valid (after sck edge) master slave t v ? ? 50 50 ns ns 11 data hold time (outputs) master slave t ho 0 0 ? ? ns ns 12 rise time input output t ri t ro ? ? t cyc ? 30 30 ns ns 13 fall time input output t fi t fo ? ? t cyc ? 30 30 ns ns
serial peripheral interface (spi) timing m68hc12b family data sheet, rev. 9.1 freescale semiconductor 329 figure 19-13. spi master timing diagram sck output sck output miso input mosi output ss (1 ) output 1 10 6 7 msb in (2) bit 6 . . . 1 lsb in msb out (2) lsb out bit 6 . . . 1 11 4 4 2 10 cpol = 0) cpol = 1 5 3 12 13 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) sck output sck output miso input mosi output 1 6 7 msb in (2) bit 6 . . . 1 lsb in master msb out (2) master lsb out bit 6 . . . 1 4 4 10 12 13 11 port data cpol = 0 cpol = 1 port data ss (1 ) output 5 2 13 12 3 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. notes: notes:
electrical specifications m68hc12b family data sheet, rev. 9.1 330 freescale semiconductor figure 19-14. spi slave timing diagram sck input sck input mosi input miso output ss input 1 10 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 11 4 4 2 8 cpol = 0 cpol = 1 5 3 13 note: not defined but normally msb of character just received slave 13 12 11 see 12 note 9 sck input sck input mosi input miso output 1 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 10 12 13 11 see cpol = 0 cpol = 1 ss input 5 2 13 12 3 note: not defined but normally lsb of character just received slave note 8 9 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1)
m68hc12b family data sheet, rev. 9.1 freescale semiconductor 331 chapter 20 mechanical specifications 20.1 introduction this section provides dimensions for the 80-pin quad flat pack (qfp).
mechanical specifications m68hc12b family data sheet, rev. 9.1 332 freescale semiconductor 20.2 80-pin quad flat pack (case 841b-02) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b-b 61 60 detail a l 41 40 80 -a- l -d- a s a-b m 0.20 d s h 0.05 a-b s 120 21 -b- b v j f n d view rotated 90 detail a b b p -a-,-b-,-d- e h g m m detail c seating plane -c- c datum plane 0.10 -h- u t r q k w x detail c dim min max millimeters a 13.90 14.10 b 13.90 14.10 c 2.15 2.45 d 0.22 0.38 e 2.00 2.40 f 0.22 0.33 g 0.65 bsc h --- 0.25 j 0.13 0.23 k 0.65 0.95 l 12.35 ref m 5 10 n 0.13 0.17 p 0.325 bsc q 0 7 r 0.13 0.30 s 16.95 17.45 t 0.13 --- u 0 --- v 16.95 17.45 w 0.35 0.45 x 1.6 ref s a-b m 0.20 d s c s a-b m 0.20 d s h 0.05 a-b datum plane -h- s a-b m 0.20 d s c s a-b m 0.20 d s c

how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual perfo rmance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004. all rights reserved. m68hc12b rev. 9.1, 07/2005
products applications technologies suppor t where to buy about freescale freescale > 16-bit microcontroll ers > hc12 automotive > 68hc912b32 68hc912b32 : microcontroller subscribe the mc68hc912b32 microcontro ller unit (mcu) is a 16-b it device composed of standard on-chip peripherals including a 16-bi t central processing unit (cpu12), 32- kbyte flash eeprom, 1-kbyte ram, 768- byte eeprom, an asynchronous serial communications interface (sci), a serial peri pheral inter-face (spi), an 8-channel timer and 16-bit pulse accumulator, a 10-bit analog-to-digital conv erter (adc), a four-channel pulse-width modulator (pwm), and a j1850-co mpatible byte data link communications module (bdlc). the chip is the first 16-bit mi crocontroller to include both byte-erasable eeprom and flash eeprom on the same device. system resource mapping, clock generation, interrupt control and bus interf acing are managed by the lite integration module (lim). the mc68hc912b32 has full 16 -bit data paths throughout, however, the multiplexed external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. block diagram 68hc912b32 features 16-bit cpu12 upward compatible with m68hc11 instruction set interrupt stacking and programmer' s model identical to m68hc11 20-bit alu instruction queue enhanced indexed addressing fuzzy logic instructions multiplexed bus single chip or expanded 16/16 wide or 16/8 narrow modes return to top 68hc912b32 parametrics serial interface timers a/d converter internal ram (byte) eeprom (byte) internal flash (byte) type channels bus frequency (max) (mhz) supply voltage (typ) (v) channels bits (bit)
1024 768 32768 j1850, sci, spi 8 8 5 8 10 pulse width modulators channels bits (bit) i o pins 2, 8 8, 16 63 68hc912b32 documentation documentation application notes id and description vendor id format size k rev # date last modified loading... loading... an2321 designing for board level electromagnetic compatibility freescale pdf 1580 1 10/18/2005 an1516 an1516 liquid level control using a pressure sensor freescale pdf 250 4 5/16/2005 an2438 adc definitions and specifications freescale pdf 497 0 2/21/2003 an2342 opto isolation circuits for in circuit debugging of 68hc9(s)12 and 68hc908 microcontrollers freescale pdf 337 0 9/25/2002 an1828 flash programming via can freescale pdf 374 1 2/13/2002 an2255 mscan low-power applications freescale pdf 261 0 2/11/2002 an2104 using background debug mode for the m68hc12 family freescale pdf 517 0 2/02/2001 an2103 local interconnect network (lin) freescale pdf 1226 0 12/01/2000
demonstration an1837 non-volatile memory technology overview freescale pdf 322 0 3/27/2000 an1836sw software files for an1836 zipped freescale zip 143 0 2/21/2000 an1050 designing for electromagnetic compatibility (emc) with hcmos microcontrollers freescale pdf 277 0 1/01/2000 an1836 flash programming for mc68hc912 microcontrollers freescale pdf 431 0 1/01/2000 an1816 using the hc912b32 to implement the distributed systems interface protocol freescale pdf 332 0 8/01/1999 an1282 board strategies for ensuring optimum frequency synthesizer performance freescale pdf 246 0 1/01/1999 an1705 noise reduction techniques for microcontroller-based systems freescale pdf 248 0 1/01/1999 an1774 interfacing the mc68hc912b32 to an lcd module freescale pdf 329 1.0 1/01/1999 an1783 determining mcu oscillator start- up parameters freescale pdf 226 1 1/01/1999 an1731 vpw j1850 multiplexing and byte data link controller (bdlc) module freescale pdf 446 0 1/01/1998 an1771 precision sine-wave tone synthesis using 8-bit mcus freescale pdf 468 0 1/01/1998 an1775 expanding digital input with an a/d converter freescale pdf 257 1 1/01/1998 an1280a using the callable routines in d- freescale pdf 243 0 1/01/1997
bug12 an1716 using m68hc12 indexed indirect addressing freescale pdf 256 1 1/01/1997 an1717 itc127 mc68hc705mc4 motion control development board freescale pdf 410 0 1/01/1997 an1718 a serial bootloader for reprogramming the mc68hc912b32 flash eeprom freescale pdf 349 0 1/01/1997 an1280 using and extending d-bug12 routines freescale pdf 247 0 1/01/1996 an1284 transporting m68hc11 code to m68hc12 devices freescale pdf 342 0 1/01/1996 an1259 system design and layout techniques for noise reduction in mcu-based systems freescale pdf 234 0 1/01/1995 an1263 designing for electromagnetic compatibility with single-chip microcontrollers freescale pdf 104 0 1/01/1995 data sheets id and description vendor id format size k rev # date last modified m68hc12b m68hc12b family data sheet freescale pdf 1945 9.1 8/17/2005 engineering bulletins id and description vendor id format size rev date last
j1850 node on a gm class 2 or chrysler pci network errata - click here for important errata information id and description vendor id format size k rev # date last modified 68hc912b32mse1 hc912b32 device information sheet: 09h91f mask sets freescale pdf 69 1 8/18/1999 68hc912b32mse2 hc912b32 device information sheet: 04j54e mask sets freescale pdf 33 2 8/18/1999 68hc912b32mse3 68hc912b32mse3 device information sheet: 0j64y mask sets freescale pdf 50 2 3/01/2001 68hc912b32mse4 hc912b32 device information sheet: mask set 4 freescale pdf 15 0 3/15/2001 fact sheets id and description vendor id format size k rev # date last modified cwdevstudfacthc08 development studio freescale pdf 48 2 5/13/2002 product change notices id and description vendor id format size k rev # date last modified loading... loading... pcn10742 klm packing change for tray devices freescale htm 38 0 3/28/2005 pcn9382 14x14x2.2 qfp new carrier tape freescale htm 106 0 12/02/2003 pcn8946 mos12 udr probe capacity flexibility freescale htm 4 0 5/27/2003 pcn8947 mos12 polyimide capacity flexibility freescale htm 5 0 5/27/2003 pcn8886 freescale htm 36 0 5/19/2003
pcn8143 tsc8/mos 12 transfer-hc12 flash devices freescale htm 14 0 10/22/2002 pcn7855 14x14 qfp assy move from shc to klm, pt 1 of 2 freescale htm 24 0 8/05/2002 pcn7856 14x14 qfp assy move from shc to klm, pt 2 of 2 freescale htm 22 0 8/05/2002 pcn7704 912b32 production ate platform change freescale htm 6 - 7/02/2002 reference manuals id and description vendor id format size k rev # date last modified cpu12rg cpu12 reference guide freescale pdf 1208 2 11/26/2001 cpu12rm hcs12 and m68hc12 cpu12 reference manual freescale pdf 3924 3 4/17/2003 roadmap id and description vendor id format size k rev # date last modified 16bitmcurd 16-bit mcu family roadmap freescale pdf 25 2.0 11/03/2004 selector guides id and description vendor id format size k rev # date last modified sg1002 sg1002 analog freescale pdf 666 0 9/29/2005 sg1006 sg1006 microcontrollers freescale pdf 1070 0 9/29/2005 sg1011 sg1011 software and development tools freescale pdf 839 0 9/29/2005 sg2000cr sg2000cr application selector guide index and cross-reference freescale pdf 130 7 7/05/2005 sg2039 application selector guide - vacuum cleaners vacuum cleaners freescale pdf 53 1 1/01/2005
return to top 68hc912b32 design tools hardware tools emulators/probes/wigglers id and description vendor id format size k rev # order availability bdi1000/bdi2000 bdi1000/bdi2000 abatron develops and produces high- quality, high-speed bdm and jtag debug tools (bdi family) for software development environments from leading vendors. abatron - - - - emul12--pc hc12 & hcs12 emulator bdm and full-featured emulators for all hcs12 and hc12 derivatives. 5v and 3.3v operation to above 25mhz bus speed. extensive support for debug through resets, power-downs, limp- home and full pll use. unlimitted number of breakpoints. nohau - - - - emul12pcbdmusb hc12 & hcs12 emulator a complete bdm emulator system with a usb interface to the pc, and support for all hcs12 and hc12 parts. nohau - - - - emul12pcbemlpt hc12 & hcs12 emulator a complete bdm emulator system with an lpt interface to the pc, and support for all hcs12 and hc12 parts. nohau - - - - ic20000 ic2000 poweremulator the ic2000 poweremulator is a universal device which supports hundreds of microcontroller families with the "swap of a pod." usb, serial, parallel and ethernet interfaces to the isys - - - -
host pc are supported. ic40000 ic4000 activeemulator the ic4000 base unit provides an "icard" interface slot so it supports all the same devices as the ic3000, plus can be set up as the base unit for the ic2000 emulator modules so it supports all the same devices as the ic2000. isys - - - - ione1xx ione onchip emulator the compact ione onchip emulator is an affordable yet rugged hardware debug solution for jtag and bdm devices. usb only, or usb/serial/ethernet versions are available. driven with winidea, isystem's ide/debug software. isys - - - - m68cyclonepro cyclone pro universal standalone in- circuit debugger/programmer freescale - - - m68multilink12 bdm multilink freescale - - - usbmultilinkbdm usb hcs08/hcs12 bdm multilink - in-circuit debugger/programmer freescale - - - evaluation/development boards and systems id and description vendor id format size k rev # order availability m68evb912b32 development tools freescale - - - scbdmpgmrs12 enhanced 16-bit bdm stand alone programmer freescale - - - programmers id and descri p tion vendor id format size rev order
programmer software is included. hassle-free serial interface. works with noice12 source level debugger. software application software code examples id and description vendor id format size k rev # order availability hc12_labcod assembly examples from training freescale zip 26 - - board support packages id and description vendor id format size k rev # order availability
ff sd 1.1 flashfile sd storage the flashfile storage system allows read and write functions for fat12 and fat16 files up to 1g byte. flashfile has a small flash and ram footprint with files readable on a pc using the fat12 and fat16 formats. inmotion - - - - operating systems id and description vendor id format size k rev # order availability cmx-rtx cmx-rtx cmx - - - - cmx00205a cmxkaware cmx - - - - cmx00400 cmx-micronet cmx - - - - cmx00400a micronet dhcp client cmx - - - - cmx00400b micronet ethernet cmx - - - cmx00400c micronet ftp cmx - - - cmx00400d micronet ppp cmx - - - - cmx00400e micronet smtp cmx - - - cmx00400f micronet tftp cmx - - - - cmx00400g micronet web server cmx - - -
cmx00500 cmx-canopen cmx - - - - cmx00600 cmx-ffs cmx - - - - cmx00601 cmx-ffs-nand cmx - - - cmx00602 cmx-ffs-fat cmx - - - cmx00603 cmx-ffs-thin cmx - - - programmers id and description vendor id format size k rev # order availability enc3e12dev encirq 3e data management suite for embedded systems encirq 3e is a rapi d application design tool that creates extremely compact, high- performance data management and database components for your embedded system. it supports all 32-bit cpus as wells as hc(s)12 mcus. encirq - - - - prog12z_auto prog12z programmer for internal and external flash/eeprom using bdm. both a gui and a command line version for production programming are provided. pemicro - - - - protocol stacks id and description vendor id format size k rev # order availability cmx-micronet cmx-micronet cmx - - - - software tools assemblers
id and description vendor id format size k rev # order availability adx-12 adx-12 macro assembler-linker and ide avocet - - - - as12srcasm c source code for freeware assembler comments freescale zip 67 1.0 - sreccvtsw sreccvtsw the zip file contains the .exe file and documentation for sreccvt; a command line tool for the conversion and reformatting of freescale s-record object files. also included is a gui interface to the command line tool for windows and mac osx. freescale zip 1626 1.0.22 - compilers id and description vendor id format size k rev # order availability cws-h12-dxp-cx codewarrior development studio for hc(s)12, data expert edition freescale - - - icc12 pro icc12 v6 pro image - - - - icc12 std icc12 v6 std image - - - - debuggers id and description vendor id format size k rev # order availability
motorola's on- chip bdm. zap uses p&e's bdm multilink cable via a pc parallel or usb port to connect and debug virtually any target system. ide (integrated development environment) id and description vendor id format size k rev # order availability cws-h12-proed-cx codewarrior development studio for hc(s)12, professional edition freescale - - - cws-h12-stded-cx codewarrior development studio for hc(s)12, standard edition freescale - - - cwx-h12-se codewarrior development studio for hc(s)12, special edition freescale - - - freemaster real-time control and debugging tool freescale - - - - ic-sw-opr winidea winidea is an integrated development environment, with project manager, editor, make and build, and high level / low level debugger, driving all of the isystem incircuit and onchip emulators. isystem u - - - - idea12 idea12 - integrated development environment for hc12/hcs12 cosmic - - - - return to top orderable parts information order part number package description tape and reel application/ qualification tier status budgetary price qty 1000+ ($us) t
mc68hc912b32cfu8 qfp 80 14*14*2.2p0.65 no - available $11.09 mc68hc912b32mfu8 qfp 80 14*14*2.2p0.65 no - available $12.20 mc68hc912b32vfu8 qfp 80 14*14*2.2p0.65 no - available $11.64 mc912b32cfu8r2 qfp 80 14*14*2.2p0.65 yes - available $11.28 mc912b32vfu8r2 qfp 80 14*14*2.2p0.65 yes - available $11.33 mchc912b32cfue8 qfp 80 14*14*2.2p0.65 no commercial, industrial, automotive available $11.09 mchc912b32mfue8 qfp 80 14*14*2.2p0.65 no commercial, industrial, automotive available $12.20 mchc912b32vfue8 qfp 80 14*14*2.2p0.65 no commercial, industrial, automotive available $11.64 - XC68HC912B32VFU8 qfp 80 14*14*2.2p0.65 no - no longer manufactured - note: ? not all orderable parts are offered thr ough our online sampling program. for further assistance in selecting a similar part from within the program, please submit a request for a sample order advice. ? refer to samples faq for more information. ? looking for an obsolete part? check our new part number search return to top related links automotive industrial control programming the freescale m68hc12 family software and hardware engi neering - freescale m68hc12
single- and multi-chip mi crocontroller interfacing embedded microcontrollers embedded microcomputer systems - real time interfacing return to top

▲Up To Search▲

Price & Availability of XC68HC912B32VFU8

	To Download XC68HC912B32VFU8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .